X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fcsb472%2Fcsb472.c;h=eac440848ab15951a24c41a394e66d7c508f14f2;hb=4a207e8b9a1ecc3e87d5a63bb5442dbcd50bd4b6;hp=c138b0d9e81bb47b33181b533888eadf0028dc36;hpb=b919a3f2981109c9f2aaafe9c692dbb99f1c6366;p=u-boot

diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
index c138b0d9e8..eac440848a 100644
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@@ -25,7 +25,7 @@
 #include <asm/processor.h>
 #include <i2c.h>
 #include <miiphy.h>
-#include <ppc4xx_enet.h>
+#include <asm/ppc4xx-emac.h>
 
 void sdram_init(void);
 
@@ -144,11 +144,11 @@ int last_stage_init(void)
 	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
 
 	/* AUTO neg */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
-			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
 
 	/* LEDs     */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
 
 	return 0; /* success */
 }