X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fdbau1x00%2Flowlevel_init.S;h=842fb76e5873e768d0a11b518ecb0aa3a4cacf8a;hb=b86d54b2c38a4beb97d580d7d9c8c6a5e57fc510;hp=14a78465f3659a0420bc18e42c3a5b85e2243315;hpb=ad88297e2f14220f34417d1304d256285887aed4;p=u-boot

diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
index 14a78465f3..842fb76e58 100644
--- a/board/dbau1x00/lowlevel_init.S
+++ b/board/dbau1x00/lowlevel_init.S
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>
@@ -9,8 +8,8 @@
 #define AU1500_SYS_ADDR		0xB1900000
 #define sys_endian		0x0038
 #define CP0_Config0		$16
-#define CPU_SCALE		((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
-#define MEM_1MS			((CFG_MHZ) * 1000)
+#define CPU_SCALE		((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS			((CONFIG_SYS_MHZ) * 1000)
 
 	.text
 	.set noreorder
@@ -586,5 +585,5 @@ noCacheJump:
 	sw	t1, 0(t0)
 	sync
 
-	j	ra
+	jr	ra
 	nop