X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fesd%2Fapc405%2Fapc405.c;h=078df001e95cdf7307532818222350bd65413b10;hb=d5ea287b02a6945c3977410e364a879dd1a555c8;hp=f7c708fe8fbb51e0843e6034cd3e06bb40d1c5e5;hpb=1bc0f14143eeffc6b37a76c9784232bf35621583;p=u-boot

diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index f7c708fe8f..078df001e9 100644
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -26,7 +26,7 @@
 #include <command.h>
 #include <malloc.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #if 0
 #define FPGA_DEBUG
@@ -63,10 +63,56 @@ unsigned char logo_bmp[] =
  */
 #include "../common/lcd.c"
 
-#include "../common/"CFG_LCD_HEADER_NAME
+#include CFG_LCD_HEADER_NAME
 #endif /* CONFIG_LCD_USED */
 
 
+int board_revision(void)
+{
+	unsigned long cntrl0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of APC405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	switch (value) {
+	case 0x00180000:
+		/* CS2==1 && CS3==1 -> version <= 1.2 */
+		return 2;
+	case 0x00080000:
+		/* CS2==0 && CS3==1 -> version 1.3 */
+		return 3;
+#if 0 /* not yet manufactured ! */
+	case 0x00100000:
+		/* CS2==1 && CS3==0 -> version 1.4 */
+		return 4;
+	case 0x00000000:
+		/* CS2==0 && CS3==0 -> version 1.5 */
+		return 5;
+#endif
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+
 int board_early_init_f (void)
 {
 	/*
@@ -122,6 +168,8 @@ int misc_init_r (void)
 {
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned short *fpga_ctrl2 =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
 	volatile unsigned char *duart0_mcr =
 		(unsigned char *)((ulong)DUART0_BA + 4);
 	volatile unsigned char *duart1_mcr =
@@ -204,6 +252,11 @@ int misc_init_r (void)
 	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 	udelay(1000); /* wait 1ms */
 
+	/*
+	 * Write board revision in FPGA
+	 */
+	*fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
+
 	/*
 	 * Enable power on PS/2 interface (with reset)
 	 */
@@ -228,8 +281,11 @@ int misc_init_r (void)
 		 logo_bmp, sizeof(logo_bmp));
 
 	/*
-	 * Enable microcontroller and setup backlight PWM controller
+	 * Reset microcontroller and setup backlight PWM controller
 	 */
+	*fpga_mode |= 0x0014;
+	for (i=0;i<10;i++)
+		udelay(1000);
 	*fpga_mode |= 0x001c;
 	*fuji_lcdbl_pwm = 0x00ff;
 
@@ -254,7 +310,8 @@ int checkboard (void)
 		puts(str);
 	}
 
-	putc ('\n');
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld\n", gd->board_type);
 
 	/*
 	 * Disable sleep mode in LXT971