X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fesd%2Fcpci405%2Fcpci405.c;h=24db8830c79d0ef8f6e8f7b271675f0f2289d695;hb=87d93a1ba2ae23550e1370adb7a3b00af0831165;hp=4c9ed2fa585ecd85923d81c28f6e24f5fa0a4b82;hpb=041a6a0c2ea8cd4039c34c5eeaf54b188c89b892;p=u-boot

diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 4c9ed2fa58..24db8830c7 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -89,7 +89,6 @@ int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
 
 /* Prototypes */
 int cpci405_version(void);
-int gunzip(void *, int, unsigned char *, unsigned long *);
 void lxt971_no_sleep(void);
 
 int board_early_init_f(void)
@@ -179,22 +178,22 @@ int board_early_init_f(void)
 	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
 #if defined(CONFIG_CPCI405_6U)
 	if (cpci405_version() == 3) {
-		mtdcr(uicpr, 0xFFFFFF99);	/* set int polarities */
+		mtdcr(UIC0PR, 0xFFFFFF99);	/* set int polarities */
 	} else {
-		mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
+		mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
 	}
 #else
-	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
+	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
 #endif
-	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,
 					 * INT0 highest priority */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }