X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fesd%2Fpci405%2Fpci405.c;h=e5d2273f07f478e3a9c826c98792906e6b10a98f;hb=90b0cf47eb23e5f3461d3d957f6898386907fd99;hp=a4f697409c6c4c0076ed307bb7d653d9cda62b09;hpb=d69b100e7038ccf7a760dad973ec4a7a35c81e9c;p=u-boot diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index a4f697409c..e5d2273f07 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001 + * (C) Copyright 2001-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -24,20 +24,28 @@ #include #include #include -#include #include #include #include <405gp_pci.h> #include "pci405.h" +DECLARE_GLOBAL_DATA_PTR; -/* ------------------------------------------------------------------------- */ +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/ +unsigned long fpga_done_state(void); +unsigned long fpga_init_state(void); #if 0 #define FPGA_DEBUG #endif +/* predefine these here */ +#define FPGA_DONE_STATE (fpga_done_state()) +#define FPGA_INIT_STATE (fpga_init_state()) + /* fpga configuration data - generated by bin2cc */ const unsigned char fpgadata[] = { @@ -49,15 +57,91 @@ const unsigned char fpgadata[] = */ #include "../common/fpga.c" +#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE) +#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12) -/* Prototypes */ -int gunzip(void *, int, unsigned char *, int *); +#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT) +#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12) + + +int board_revision(void) +{ + unsigned long cntrl0Reg; + unsigned long value; + + /* + * Get version of PCI405 board from GPIO's + */ + + /* + * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x03000000); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200); + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x00100200; /* get config bits */ + + /* + * Restore GPIO settings + */ + mtdcr(cntrl0, cntrl0Reg); + + switch (value) { + case 0x00100200: + /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */ + return 1; + case 0x00000200: + /* CS2==0 && IRQ5==1 -> version 1.2 */ + return 2; + case 0x00000000: + /* CS2==0 && IRQ5==0 -> version 1.3 */ + return 3; +#if 0 /* not yet manufactured ! */ + case 0x00100000: + /* CS2==1 && IRQ5==0 -> version 1.4 */ + return 4; +#endif + default: + /* should not be reached! */ + return 0; + } +} + + +unsigned long fpga_done_state(void) +{ + if (gd->board_type < 2) { + return FPGA_DONE_STATE_V11; + } else { + return FPGA_DONE_STATE_V12; + } +} -int board_pre_init (void) +unsigned long fpga_init_state(void) +{ + if (gd->board_type < 2) { + return FPGA_INIT_STATE_V11; + } else { + return FPGA_INIT_STATE_V12; + } +} + + +int board_early_init_f (void) { unsigned long cntrl0Reg; + /* + * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) + */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ + out32(GPIO0_OR, 0); /* pull prg low */ + /* * IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 16 405GP internally generated; active low; level sensitive @@ -84,6 +168,16 @@ int board_pre_init (void) cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x00008000); + /* + * Setup GPIO pins (CS6+CS7 as GPIO) + */ + mtdcr(cntrl0, cntrl0Reg | 0x00300000); + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + return 0; } @@ -103,7 +197,6 @@ int misc_init_r (void) int status; int index; int i; - struct pci_config_regs *pci_regs; unsigned int *ptr; unsigned int *magic; @@ -113,7 +206,7 @@ int misc_init_r (void) */ dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) { + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -179,7 +272,7 @@ int misc_init_r (void) * Rewrite pci config regs (only after soft-reset with magic set) */ ptr = (unsigned int *)PCI_REGS_ADDR; - if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { + if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { puts("Restoring PCI Configurations Regs!\n"); ptr = (unsigned int *)PCI_REGS_ADDR + 1; for (i=0; i<0x40; i+=4) { @@ -187,10 +280,32 @@ int misc_init_r (void) } } mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - + *magic = 0; /* clear pci reconfig magic again */ } +#if 1 /* test-only */ + /* + * Decrease PLB latency timeout and reduce priority of the PCI bridge master + */ +#define PCI0_BRDGOPT1 0x4a + pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); +/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */ + +#define plb0_acr 0x87 + /* + * Enable fairness and high bus utilization + */ + mtdcr(plb0_acr, 0x98000000); + +#if 0 /* test-only */ + printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */ +/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */ + mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000); +#endif +/* printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */ +#endif + free(dst); return (0); } @@ -202,7 +317,7 @@ int misc_init_r (void) int checkboard (void) { - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); puts ("Board: "); @@ -212,7 +327,31 @@ int checkboard (void) } else { puts (str); } - putc ('\n'); + + gd->board_type = board_revision(); + printf(" (Rev 1.%ld", gd->board_type); + + if (gd->board_type >= 2) { + unsigned long cntrl0Reg; + unsigned long value; + + /* + * Setup GPIO pins (Trace/GPIO1 to GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg & ~0x08000000); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000); + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x40000000; /* get config bits */ + if (value) { + puts(", 33 MHz PCI"); + } else { + puts(", 66 Mhz PCI"); + } + } + + puts(")\n"); return 0; } @@ -249,3 +388,48 @@ int testdram (void) } /* ------------------------------------------------------------------------- */ +int wpeeprom(int wp) +{ + int wp_state = wp; + volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404; + + if (wp == 1) { + *uart1_mcr &= ~0x02; + } else if (wp == 0) { + *uart1_mcr |= 0x02; + } else { + if (*uart1_mcr & 0x02) { + wp_state = 0; + } else { + wp_state = 1; + } + } + return wp_state; +} + +int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int wp = -1; + if (argc >= 2) { + if (argv[1][0] == '1') { + wp = 1; + } else if (argv[1][0] == '0') { + wp = 0; + } + } + + wp = wpeeprom(wp); + printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED"); + return 0; +} + +U_BOOT_CMD( + wpeeprom, 2, 1, do_wpeeprom, + "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n", + "wpeeprom\n" + " - check I2C EEPROM write protection state\n" + "wpeeprom 1\n" + " - enable I2C EEPROM write protection\n" + "wpeeprom 0\n" + " - disable I2C EEPROM write protection\n" + );