X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fevb64260%2Feth.c;h=eb87edcbfec7d8e322e3cb32047e8a1711e55ff7;hb=a53f4a29ac62a2e83d35a4a7b6d6969cf95a5902;hp=a248cadf73c7a87db9ba8d732011451960e71f97;hpb=84bd92bdda05e6aaae3150ed6ef957b3a67398b7;p=u-boot diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index a248cadf73..eb87edcbfe 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -27,11 +27,12 @@ Skeleton NIC driver for Etherboot #include #include #include +#include #include "eth.h" #include "eth_addrtbl.h" -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#if defined(CONFIG_CMD_NET) #define GT6426x_ETH_BUF_SIZE 1536 @@ -85,12 +86,17 @@ static const char ether_port_phy_addr[3]={0,1,2}; static const char ether_port_phy_addr[3]={4,5,6}; #endif +/* MII PHY access routines are common for all i/f, use gal_ent0 */ +#define GT6426x_MII_DEVNAME "gal_enet0" + +int gt6426x_miiphy_read(const char *devname, unsigned char phy, + unsigned char reg, unsigned short *val); static inline unsigned short miiphy_read_ret(unsigned short phy, unsigned short reg) { unsigned short val; - miiphy_read(phy,reg,&val); + gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val); return val; } @@ -121,31 +127,32 @@ static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr) #endif if(icr&0x10000000) { +#ifdef DEBUG unsigned int psr; + psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); -#ifdef DEBUG printf("PHY state change:\n" " GT:%s:%s:%s:%s\n", - psr&1?"100":" 10", - psr&8?" Link":"nLink", - psr&2?"FD":"HD", - psr&4?" FC":"nFC"); + psr & 1 ? "100" : " 10", + psr & 8 ? " Link" : "nLink", + psr & 2 ? "FD" : "HD", + psr & 4 ? " FC" : "nFC"); #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */ { - unsigned short mii_11; - mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11); - - printf(" mii:%s:%s:%s:%s %s:%s %s\n", - mii_11&(1<<14)?"100":" 10", - mii_11&(1<<10)?" Link":"nLink", - mii_11&(1<<9)?"FD":"HD", - mii_11&(1<<4)?" FC":"nFC", - - mii_11&(1<<7)?"ANc":"ANnc", - mii_11&(1<<8)?"AN":"Manual", - "" - ); + unsigned short mii_11; + mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11); + + printf(" mii:%s:%s:%s:%s %s:%s %s\n", + mii_11 & (1 << 14) ? "100" : " 10", + mii_11 & (1 << 10) ? " Link" : "nLink", + mii_11 & (1 << 9) ? "FD" : "HD", + mii_11 & (1 << 4) ? " FC" : "nFC", + + mii_11 & (1 << 7) ? "ANc" : "ANnc", + mii_11 & (1 << 8) ? "AN" : "Manual", + "" + ); } #endif /* CONFIG_INTEL_LXT97X */ #endif /* DEBUG */ @@ -158,7 +165,7 @@ gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr) int eth_len=0; char *eth_data; - eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)]; + eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)]; INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); @@ -247,7 +254,7 @@ gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s) #ifdef DEBUG unsigned int old_command_stat,old_psr; #endif - eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn]; + eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn]; /* wait for tx to be ready */ INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); @@ -339,8 +346,8 @@ gt6426x_eth_disable(void *v) MII utilities - write: write to an MII register via SMI ***************************************************************************/ int -miiphy_write(unsigned char phy, unsigned char reg, - unsigned short data) +gt6426x_miiphy_write(const char *devname, unsigned char phy, + unsigned char reg, unsigned short data) { unsigned int temp= (reg<<21) | (phy<<16) | data; @@ -354,8 +361,8 @@ miiphy_write(unsigned char phy, unsigned char reg, MII utilities - read: read from an MII register via SMI ***************************************************************************/ int -miiphy_read(unsigned char phy, unsigned char reg, - unsigned short *val) +gt6426x_miiphy_read(const char *devname, unsigned char phy, + unsigned char reg, unsigned short *val) { unsigned int temp= (reg<<21) | (phy<<16) | 1<<26; @@ -416,24 +423,24 @@ gt6426x_dump_mii(bd_t *bis, unsigned short phy) static void check_phy_state(struct eth_dev_s *p) { - int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR); + int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR); int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); - if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) { - int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) & - miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR); + if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) { + int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) & + miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA); int want; - if (nego & PHY_ANLPAR_TXFD) { + if (nego & LPA_100FULL) { want = 0x3; printf("MII: 100Base-TX, Full Duplex\n"); - } else if (nego & PHY_ANLPAR_TX) { + } else if (nego & LPA_100HALF) { want = 0x1; printf("MII: 100Base-TX, Half Duplex\n"); - } else if (nego & PHY_ANLPAR_10FD) { + } else if (nego & LPA_10FULL) { want = 0x2; printf("MII: 10Base-T, Full Duplex\n"); - } else if (nego & PHY_ANLPAR_10) { + } else if (nego & LPA_10HALF) { want = 0x0; printf("MII: 10Base-T, Half Duplex\n"); } else { @@ -444,7 +451,7 @@ check_phy_state(struct eth_dev_s *p) if ((psr & 0x3) != want) { printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n", psr & 0x3, want); - miiphy_write(ether_port_phy_addr[p->dev],0, + miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0, miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9)); udelay(10000); /* the EVB's GT takes a while to notice phy went down and up */ @@ -490,7 +497,7 @@ gt6426x_eth_probe(void *v, bd_t *bis) led 2: 0xc=link/rxact led 3: 0x2=rxact (N/C) strch: 0,2=30 ms, enable */ - miiphy_write(ether_port_phy_addr[p->dev], 20, 0x1c22); + miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22); /* 2.7ns port rise time */ /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */ @@ -524,7 +531,7 @@ gt6426x_eth_probe(void *v, bd_t *bis) #endif /* 31 28 27 24 23 20 19 16 - * 0000 0000 0000 0000 [0004] + * 0000 0000 0000 0000 [0004] * 15 12 11 8 7 4 3 0 * 1000 1101 0000 0000 [4d00] * 20 - 0=MII 1=RMII @@ -679,7 +686,7 @@ gt6426x_eth_initialize(bd_t *bis) return; } - /* must be less than NAMESIZE (16) */ + /* must be less than sizeof(dev->name) */ sprintf(dev->name, "gal_enet%d", devnum); #ifdef DEBUG @@ -702,7 +709,7 @@ gt6426x_eth_initialize(bd_t *bis) return; } - temp = getenv_r (s, buf, sizeof(buf)); + temp = getenv_f(s, buf, sizeof(buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG @@ -792,6 +799,11 @@ gt6426x_eth_initialize(bd_t *bis) eth_register(dev); +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, + gt6426x_miiphy_read, gt6426x_miiphy_write); +#endif } + } -#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */ +#endif