X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fevb64260%2Fpci.c;h=582f24c67bbc775940fee2f0d35563f9896aa15e;hb=01815c2d06c5b838f2cd536703e47bd2c9148194;hp=9cd9722eec5e3d72e1f95612eb4bc5369c71fd67;hpb=198ea9e294e38cea49f9f2d9b911bdfdd20e48dc;p=u-boot

diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c
index 9cd9722eec..582f24c67b 100644
--- a/board/evb64260/pci.c
+++ b/board/evb64260/pci.c
@@ -629,6 +629,7 @@ static void gt_setup_ide (struct pci_controller *hose,
 	}
 }
 
+#ifndef CONFIG_P3G4
 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 {
 	unsigned char pin, irq;
@@ -642,6 +643,7 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
 	}
 }
+#endif
 
 struct pci_config_table gt_config_table[] = {
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
@@ -651,12 +653,16 @@ struct pci_config_table gt_config_table[] = {
 };
 
 struct pci_controller pci0_hose = {
+#ifndef CONFIG_P3G4
 	fixup_irq:gt_fixup_irq,
+#endif
 	config_table:gt_config_table,
 };
 
 struct pci_controller pci1_hose = {
+#ifndef CONFIG_P3G4
 	fixup_irq:gt_fixup_irq,
+#endif
 	config_table:gt_config_table,
 };
 
@@ -669,14 +675,14 @@ void pci_init_board (void)
 	local_buses[0] = pci0_hose.first_busno;
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -692,8 +698,10 @@ void pci_init_board (void)
 
 	pci_register_hose (&pci0_hose);
 
+#ifndef CONFIG_P3G4
 	pciArbiterEnable (PCI_HOST0);
 	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+#endif
 
 	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
 	command |= PCI_COMMAND_MASTER;
@@ -712,14 +720,14 @@ void pci_init_board (void)
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -735,8 +743,10 @@ void pci_init_board (void)
 
 	pci_register_hose (&pci1_hose);
 
+#ifndef CONFIG_P3G4
 	pciArbiterEnable (PCI_HOST1);
 	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+#endif
 
 	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
 	command |= PCI_COMMAND_MASTER;