X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fcommon%2Fpfuze.c;h=69afa835623a30109014497a38b94f621df4f7de;hb=e5f96a872b7da006b55d1fcdfd602b15a3056497;hp=2cd17944298b91b49d7b330e4b3c23af1786e0c2;hpb=21008ad6384170767041f1608975473c5ffa7fc7;p=u-boot diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c index 2cd1794429..69afa83562 100644 --- a/board/freescale/common/pfuze.c +++ b/board/freescale/common/pfuze.c @@ -5,9 +5,49 @@ */ #include +#include #include #include +#ifndef CONFIG_DM_PMIC_PFUZE100 +int pfuze_mode_init(struct pmic *p, u32 mode) +{ + unsigned char offset, i, switch_num; + u32 id; + int ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = id & 0xf; + + if (id == 0) { + switch_num = 6; + offset = PFUZE100_SW1CMODE; + } else if (id == 1) { + switch_num = 4; + offset = PFUZE100_SW2MODE; + } else { + printf("Not supported, id=%d\n", id); + return -EINVAL; + } + + ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + if (ret < 0) { + printf("Set SW1AB mode error!\n"); + return ret; + } + + for (i = 0; i < switch_num - 1; i++) { + ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + if (ret < 0) { + printf("Set switch 0x%x mode error!\n", + offset + i * SWITCH_SIZE); + return ret; + } + } + + return ret; +} + struct pmic *pfuze_common_init(unsigned char i2cbus) { struct pmic *p; @@ -33,10 +73,10 @@ struct pmic *pfuze_common_init(unsigned char i2cbus) pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); + pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); + pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); @@ -52,3 +92,4 @@ struct pmic *pfuze_common_init(unsigned char i2cbus) return p; } +#endif