X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fcommon%2Fpfuze.c;h=69afa835623a30109014497a38b94f621df4f7de;hb=ed2530d0963196a7175058ed9b5e6cbc29822f7f;hp=4980bf7b0089528db6f0dc5a4c45d4db99d4eaa5;hpb=7428f55c94ac51214038a3882630ddb89520e42e;p=u-boot

diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 4980bf7b00..69afa83562 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -9,10 +9,12 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 
+#ifndef CONFIG_DM_PMIC_PFUZE100
 int pfuze_mode_init(struct pmic *p, u32 mode)
 {
 	unsigned char offset, i, switch_num;
-	u32 id, ret;
+	u32 id;
+	int ret;
 
 	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
 	id = id & 0xf;
@@ -71,10 +73,10 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
 	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 
 	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
-	pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
 	reg &= ~SW1xCONF_DVSSPEED_MASK;
 	reg |= SW1xCONF_DVSSPEED_4US;
-	pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 
 	/* Set SW1C standby voltage to 0.975V */
 	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
@@ -90,3 +92,4 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
 
 	return p;
 }
+#endif