X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fcommon%2Fqixis.c;h=a49e3006d9d7897358cfa4d6d7baecf401df99e5;hb=4eef93da262048eb1118e726b3ec5b8ebd3c6c91;hp=6cd7e5108a60da5bef6181bb002c98f39aa4025c;hpb=ae6b03fefc1a8b27d834ef12e0a586f4237fdb1f;p=u-boot diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 6cd7e5108a..a49e3006d9 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -2,20 +2,31 @@ * Copyright 2011 Freescale Semiconductor * Author: Shengzhou Liu * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * SPDX-License-Identifier: GPL-2.0+ * * This file provides support for the QIXIS of some Freescale reference boards. - * */ #include #include #include +#include +#include #include "qixis.h" +#ifdef CONFIG_SYS_I2C_FPGA_ADDR +u8 qixis_read_i2c(unsigned int reg) +{ + return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); +} + +void qixis_write_i2c(unsigned int reg, u8 value) +{ + u8 val = value; + i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); +} +#endif + u8 qixis_read(unsigned int reg) { void *p = (void *)QIXIS_BASE; @@ -30,24 +41,110 @@ void qixis_write(unsigned int reg, u8 value) out_8(p + reg, value); } +u16 qixis_read_minor(void) +{ + u16 minor; + + /* this data is in little endian */ + QIXIS_WRITE(tagdata, 5); + minor = QIXIS_READ(tagdata); + QIXIS_WRITE(tagdata, 6); + minor += QIXIS_READ(tagdata) << 8; + + return minor; +} + +char *qixis_read_time(char *result) +{ + time_t time = 0; + int i; + + /* timestamp is in 32-bit big endian */ + for (i = 8; i <= 11; i++) { + QIXIS_WRITE(tagdata, i); + time = (time << 8) + QIXIS_READ(tagdata); + } + + return ctime_r(&time, result); +} + +char *qixis_read_tag(char *buf) +{ + int i; + char tag, *ptr = buf; + + for (i = 16; i <= 63; i++) { + QIXIS_WRITE(tagdata, i); + tag = QIXIS_READ(tagdata); + *(ptr++) = tag; + if (!tag) + break; + } + if (i > 63) + *ptr = '\0'; + + return buf; +} + +/* + * return the string of binary of u8 in the format of + * 1010 10_0. The masked bit is filled as underscore. + */ +const char *byte_to_binary_mask(u8 val, u8 mask, char *buf) +{ + char *ptr; + int i; + + ptr = buf; + for (i = 0x80; i > 0x08 ; i >>= 1, ptr++) + *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); + *(ptr++) = ' '; + for (i = 0x08; i > 0 ; i >>= 1, ptr++) + *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); + + *ptr = '\0'; + + return buf; +} + +#ifdef QIXIS_RST_FORCE_MEM +void board_assert_mem_reset(void) +{ + u8 rst; + + rst = QIXIS_READ(rst_frc[0]); + if (!(rst & QIXIS_RST_FORCE_MEM)) + QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM); +} + +void board_deassert_mem_reset(void) +{ + u8 rst; + + rst = QIXIS_READ(rst_frc[0]); + if (rst & QIXIS_RST_FORCE_MEM) + QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM); +} +#endif + void qixis_reset(void) { - QIXIS_WRITE(rst_ctl, 0x83); + QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); } void qixis_bank_reset(void) { - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); } -/* Set the boot bank to the power-on default bank0 */ +/* Set the boot bank to the power-on default bank */ void clear_altbank(void) { u8 reg; reg = QIXIS_READ(brdcfg[0]); - reg = reg & ~QIXIS_LBMAP_MASK; + reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK; QIXIS_WRITE(brdcfg[0], reg); } @@ -61,7 +158,6 @@ void set_altbank(void) QIXIS_WRITE(brdcfg[0], reg); } -#ifdef DEBUG static void qixis_dump_regs(void) { int i; @@ -85,13 +181,20 @@ static void qixis_dump_regs(void) printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); printf("present = %02x\n", QIXIS_READ(present)); + printf("present2 = %02x\n", QIXIS_READ(present2)); printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); - printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2)); } -#endif + +static void __qixis_dump_switch(void) +{ + puts("Reverse engineering switch is not implemented for this board\n"); +} + +void qixis_dump_switch(void) + __attribute__((weak, alias("__qixis_dump_switch"))); int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -115,22 +218,20 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) for (i = 0; i < ARRAY_SIZE(period); i++) { if (strcmp(argv[2], period[i]) == 0) { /* disable watchdog */ - QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08); + QIXIS_WRITE(rcfg_ctl, + rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); QIXIS_WRITE(watch, ((i<<2) - 1)); QIXIS_WRITE(rcfg_ctl, rcfg); return 0; } } - } - -#ifdef DEBUG - else if (strcmp(argv[1], "dump") == 0) { + } else if (strcmp(argv[1], "dump") == 0) { qixis_dump_regs(); return 0; - } -#endif - - else { + } else if (strcmp(argv[1], "switch") == 0) { + qixis_dump_switch(); + return 0; + } else { printf("Invalid option: %s\n", argv[1]); return 1; } @@ -145,7 +246,6 @@ U_BOOT_CMD( "qixis_reset altbank - reset to alternate bank\n" "qixis watchdog - set the watchdog period\n" " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" -#ifdef DEBUG "qixis_reset dump - display the QIXIS registers\n" -#endif + "qixis_reset switch - display switch\n" );