X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fcorenet_ds%2Fp4080ds_ddr.c;h=844e1d736a7a54752105a546cf86cbee70469255;hb=2988eac70ead3720f9ec85a239cd06b2f7246683;hp=4ad89ff48a970279d828c10696df1c5080075028;hpb=37a3bda0c9c8a2ffbf7e2a9e121177a3385a0626;p=u-boot

diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
index 4ad89ff48a..844e1d736a 100644
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -9,12 +9,6 @@
 #include <common.h>
 #include <asm/fsl_ddr_sdram.h>
 
-#define DATARATE_800MHZ			800000000
-#define DATARATE_900MHZ			900000000
-#define DATARATE_1000MHZ		1000000000
-#define DATARATE_1200MHZ		1200000000
-#define DATARATE_1300MHZ		1300000000
-
 #define CONFIG_SYS_DDR_TIMING_3_1200	0x01030000
 #define CONFIG_SYS_DDR_TIMING_0_1200	0xCC550104
 #define CONFIG_SYS_DDR_TIMING_1_1200	0x868FAA45
@@ -340,17 +334,17 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
 };
 
 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-	{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800},
-	{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900},
-	{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000},
-	{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200},
+	{750, 850, &ddr_cfg_regs_800},
+	{850, 950, &ddr_cfg_regs_900},
+	{950, 1050, &ddr_cfg_regs_1000},
+	{1050, 1250, &ddr_cfg_regs_1200},
 	{0, 0, NULL}
 };
 
 fixed_ddr_parm_t fixed_ddr_parm_1[] = {
-	{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd},
-	{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd},
-	{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd},
-	{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd},
+	{750, 850, &ddr_cfg_regs_800_2nd},
+	{850, 950, &ddr_cfg_regs_900_2nd},
+	{950, 1050, &ddr_cfg_regs_1000_2nd},
+	{1050, 1250, &ddr_cfg_regs_1200_2nd},
 	{0, 0, NULL}
 };