X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fls1043aqds%2Fddr.h;h=ad709ba216b9565fd8c7ded1b30cfd84676f9514;hb=6e2941d787819ae1221d7f8295fa67d2ba94a913;hp=8adb660012596837e399af918085ea5926c9b0c2;hpb=f1993ca066100fcaba7d49fecae0ef604e5807e2;p=u-boot

diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h
index 8adb660012..ad709ba216 100644
--- a/board/freescale/ls1043aqds/ddr.h
+++ b/board/freescale/ls1043aqds/ddr.h
@@ -7,6 +7,8 @@
 #ifndef __DDR_H__
 #define __DDR_H__
 
+extern void erratum_a008850_post(void);
+
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
@@ -32,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E0A,},
-	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
-	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+	{2,  1666, 0,  8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0,  8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0,  8,     6, 0x0708090B, 0x0C0D0E0A,},
+	{1,  1900, 0,  8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0,  8,    10, 0x0B0C0D0C, 0x0E0F110E,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
-	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 #else
 #error DDR type not defined
 #endif