X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fm5253demo%2Fm5253demo.c;h=4772074d81fb94e55672804ecd2235c492f5b33d;hb=8d1f268204b07e172f3cb5cee0a3974d605b0b98;hp=2eb6a0444f9e6be8763b5d91896aca3a5f762b24;hpb=ce0eb70333331da6942167c41e6841c8c7994a33;p=u-boot

diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 2eb6a0444f..4772074d81 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -26,6 +26,7 @@
 
 #include <common.h>
 #include <asm/immap.h>
+#include <netdev.h>
 
 int checkboard(void)
 {
@@ -45,7 +46,7 @@ phys_size_t initdram(int board_type)
 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
 		u32 RC, temp;
 
-		RC = (CFG_CLK / 1000000) >> 1;
+		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
 		RC = (RC * 15) >> 4;
 
 		/* Initialize DRAM Control Register: DCR */
@@ -56,7 +57,7 @@ phys_size_t initdram(int board_type)
 		__asm__("nop");
 
 		/* Initialize DMR0 */
-		dramsize = (CFG_SDRAM_SIZE << 20);
+		dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
 		temp = (dramsize - 1) & 0xFFFC0000;
 		mbar_writeLong(MCFSIM_DMR0, temp | 1);
 		__asm__("nop");
@@ -65,7 +66,7 @@ phys_size_t initdram(int board_type)
 		__asm__("nop");
 
 		/* Write to this block to initiate precharge */
-		*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
 		__asm__("nop");
 
 		/* Set RE bit in DACR */
@@ -81,7 +82,7 @@ phys_size_t initdram(int board_type)
 			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
 		__asm__("nop");
 
-		*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
 	}
 
 	return dramsize;
@@ -104,7 +105,7 @@ int ide_preinit(void)
 
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
+	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
@@ -121,7 +122,7 @@ void ide_set_reset(int idereset)
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
 
 #define CALC_TIMING(t) (t + period - 1) / period
-		period = 1000000000 / (CFG_CLK / 2);	/* period in ns */
+		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
 		ata->t1 = CALC_TIMING(piotms[2][0]);
@@ -138,3 +139,11 @@ void ide_set_reset(int idereset)
 	}
 }
 #endif				/* CONFIG_CMD_IDE */
+
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif