X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fm5282evb%2Fm5282evb.c;h=b0c9fc83f2729f06b69b2b705221396a3a29104e;hb=e845f9006a617eb4449e7dea9fd7493438db804e;hp=50e5e77368651498f5209438bc4984d5505c6bba;hpb=10db3a17a278dd3a27668b31cb32cdd1476e9513;p=u-boot

diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index 50e5e77368..b0c9fc83f2 100644
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -36,7 +36,7 @@ phys_size_t initdram (int board_type)
 {
 	u32 dramsize, i, dramclk;
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
 			break;
@@ -45,27 +45,31 @@ phys_size_t initdram (int board_type)
 
 	if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
 	{
-		dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
 
 		/* Initialize DRAM Control Register: DCR */
 		MCFSDRAMC_DCR = (0
 			| MCFSDRAMC_DCR_RTIM_6
 			| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
+		asm("nop");
 
 		/* Initialize DACR0 */
 		MCFSDRAMC_DACR0 = (0
-			| MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
+			| MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
 			| MCFSDRAMC_DACR_CASL(1)
 			| MCFSDRAMC_DACR_CBM(3)
 			| MCFSDRAMC_DACR_PS_32);
+		asm("nop");
 
 		/* Initialize DMR0 */
 		MCFSDRAMC_DMR0 = (0
 			| ((dramsize - 1) & 0xFFFC0000)
 			| MCFSDRAMC_DMR_V);
+		asm("nop");
 
 		/* Set IP (bit 3) in DACR */
 		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+		asm("nop");
 
 		/* Wait 30ns to allow banks to precharge */
 		for (i = 0; i < 5; i++) {
@@ -73,10 +77,12 @@ phys_size_t initdram (int board_type)
 		}
 
 		/* Write to this block to initiate precharge */
-		*(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+		asm("nop");
 
 		/* Set RE (bit 15) in DACR */
 		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+		asm("nop");
 
 		/* Wait for at least 8 auto refresh cycles to occur */
 		for (i = 0; i < 2000; i++) {
@@ -85,9 +91,10 @@ phys_size_t initdram (int board_type)
 
 		/* Finish the configuration by issuing the IMRS. */
 		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
+		asm("nop");
 
 		/* Write to the SDRAM Mode Register */
-		*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
 	return dramsize;
 }