X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8315erdb%2Fmpc8315erdb.c;h=e6f091fd2f4c6060d1c1aa9dc0e465c267ecc30b;hb=3e1b36bd584228b0a8070c8b63351aefda652523;hp=7af36ddb9b70e8977263d145581b50d2639985a1;hpb=9cfff9e9d4d9dbb9bb428cea3fa2cda3b3e593ad;p=u-boot diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index 7af36ddb9b..e6f091fd2f 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -4,38 +4,26 @@ * Author: Scott Wood * Dave Liu * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include -#if defined(CONFIG_OF_LIBFDT) #include -#endif +#include #include #include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) gd->flags |= GD_FLG_SILENT; @@ -43,12 +31,14 @@ int board_early_init_f(void) return 0; } +#ifndef CONFIG_NAND_SPL + static u8 read_board_info(void) { u8 val8; i2c_set_bus_num(0); - if (i2c_read(CFG_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) + if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) return val8; else return 0; @@ -76,32 +66,64 @@ int checkboard(void) static struct pci_region pci_regions[] = { { - bus_start: CFG_PCI_MEM_BASE, - phys_start: CFG_PCI_MEM_PHYS, - size: CFG_PCI_MEM_SIZE, + bus_start: CONFIG_SYS_PCI_MEM_BASE, + phys_start: CONFIG_SYS_PCI_MEM_PHYS, + size: CONFIG_SYS_PCI_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI_MMIO_BASE, - phys_start: CFG_PCI_MMIO_PHYS, - size: CFG_PCI_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI_MMIO_BASE, + phys_start: CONFIG_SYS_PCI_MMIO_PHYS, + size: CONFIG_SYS_PCI_MMIO_SIZE, flags: PCI_REGION_MEM }, { - bus_start: CFG_PCI_IO_BASE, - phys_start: CFG_PCI_IO_PHYS, - size: CFG_PCI_IO_SIZE, + bus_start: CONFIG_SYS_PCI_IO_BASE, + phys_start: CONFIG_SYS_PCI_IO_PHYS, + size: CONFIG_SYS_PCI_IO_SIZE, flags: PCI_REGION_IO } }; +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile sysconf83xx_t *sysconf = &immr->sysconf; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile law83xx_t *pcie_law = sysconf->pcielaw; struct pci_region *reg[] = { pci_regions }; - int warmboot; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; /* Enable all 3 PCI_CLK_OUTPUTs. */ clk->occr |= 0xe0000000; @@ -109,24 +131,114 @@ void pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; - warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; + mpc83xx_pci_init(1, reg); + + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - mpc83xx_pci_init(1, reg, warmboot); + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg); } #if defined(CONFIG_OF_BOARD_SETUP) +void fdt_tsec1_fixup(void *fdt, bd_t *bd) +{ + const char disabled[] = "disabled"; + const char *path; + int ret; + + if (hwconfig_arg_cmp("board_type", "tsec1")) { + return; + } else if (!hwconfig_arg_cmp("board_type", "ulpi")) { + printf("NOTICE: No or unknown board_type hwconfig specified.\n" + " Assuming board with TSEC1.\n"); + return; + } + + ret = fdt_path_offset(fdt, "/aliases"); + if (ret < 0) { + printf("WARNING: can't find /aliases node\n"); + return; + } + + path = fdt_getprop(fdt, ret, "ethernet0", NULL); + if (!path) { + printf("WARNING: can't find ethernet0 alias\n"); + return; + } + + do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); +} + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + fdt_fixup_dr_usb(blob, bd); + fdt_tsec1_fixup(blob, bd); } #endif + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Initialize TSECs first */ + return pci_eth_init(bis); +} + +#else /* CONFIG_NAND_SPL */ + +int checkboard(void) +{ + puts("Board: Freescale MPC8315ERDB\n"); + return 0; +} + +void board_init_f(ulong bootflag) +{ + board_early_init_f(); + NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + puts("NAND boot... "); + init_timebase(); + initdram(0); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (gd->flags & GD_FLG_SILENT) + return; + + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); +} + +#endif /* CONFIG_NAND_SPL */