X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8360emds%2Fmpc8360emds.c;h=ac96163aa47e2577be512f4a18361044684bcd4f;hb=362f16b1e9e94024a511adae9977d145ef942b50;hp=538a556c6033fc36b1320381b5fe74b149cbd398;hpb=651d96f7e4c84adcdb98ef07ec878c20326e3359;p=u-boot diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 538a556c60..ac96163aa4 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -1,38 +1,33 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc. * Dave Liu * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include -#include #include +#include #if defined(CONFIG_PCI) #include #endif -#if defined(CONFIG_SPD_EEPROM) #include -#else #include -#endif -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) +#include +#include +#include +#if defined(CONFIG_OF_LIBFDT) #include #endif +#include +#include #if defined(CONFIG_PQ_MDS_PIB) #include "../common/pq-mds-pib.h" #endif +#include "../../../drivers/qe/uec.h" const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ @@ -95,59 +90,116 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; -int board_early_init_f(void) +/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */ +static int board_handle_erratum2(void) { + const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - u8 *bcsr = (u8 *)CFG_BCSR; - const immap_t *immr = (immap_t *)CFG_IMMR; + return REVID_MAJOR(immr->sysconf.spridr) == 2 && + REVID_MINOR(immr->sysconf.spridr) == 1; +} + +int board_early_init_f(void) +{ + const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; /* Enable flash write */ bcsr[0xa] &= ~0x04; - /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */ - if (immr->sysconf.spridr == SPR_8360_REV20 || - immr->sysconf.spridr == SPR_8360E_REV20 || - immr->sysconf.spridr == SPR_8360_REV21 || - immr->sysconf.spridr == SPR_8360E_REV21) + /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */ + if (REVID_MAJOR(immr->sysconf.spridr) == 2) bcsr[0xe] = 0x30; /* Enable second UART */ bcsr[0x9] &= ~0x01; + if (board_handle_erratum2()) { + void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8); + + /* + * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) + * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) + */ + setbits_be32(immap, 0x0c003000); + + /* + * IMMR + 0x14AC[20:27] = 10101010 + * (data delay for both UCC's) + */ + clrsetbits_be32(immap + 4, 0xff0, 0xaa0); + } return 0; } int board_early_init_r(void) { + gd_t *gd; #ifdef CONFIG_PQ_MDS_PIB pib_init(); #endif + /* + * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB + * So re-setup PCI MEM space used BAT5 after relocated to DDR + */ + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); + write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); + } + return 0; } -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#ifdef CONFIG_UEC_ETH +static uec_info_t uec_info[] = { +#ifdef CONFIG_UEC_ETH1 + STD_UEC_INFO(1), +#endif +#ifdef CONFIG_UEC_ETH2 + STD_UEC_INFO(2), +#endif +}; + +int board_eth_init(bd_t *bd) +{ + if (board_handle_erratum2()) { + int i; + + for (i = 0; i < ARRAY_SIZE(uec_info); i++) { + uec_info[i].enet_interface_type = + PHY_INTERFACE_MODE_RGMII_RXID; + uec_info[i].speed = SPEED_1000; + } + } + return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); +} +#endif /* CONFIG_UEC_ETH */ + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); -void sdram_init(void); +static int sdram_init(unsigned int base); -long int initdram(int board_type) +phys_size_t initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; + u32 lbc_sdram_size; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else msize = fixed_sdram(); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize DDR ECC byte */ @@ -156,7 +208,9 @@ long int initdram(int board_type) /* * Initialize SDRAM if it is on local bus. */ - sdram_init(); + lbc_sdram_size = sdram_init(msize * 1024 * 1024); + if (!msize) + msize = lbc_sdram_size; /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); @@ -168,56 +222,66 @@ long int initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CFG_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; + u32 ddr_size_log2 = __ilog2(ddr_size); + u32 half_ddr_size = ddr_size >> 1; + + im->sysconf.ddrlaw[0].bar = + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); +#if (CONFIG_SYS_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif #ifdef CONFIG_DDR_II - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else - im->ddr.csbnds[0].csbnds = 0x00000007; - im->ddr.csbnds[1].csbnds = 0x0008000f; - - im->ddr.cs_config[0] = CFG_DDR_CONFIG; - im->ddr.cs_config[1] = CFG_DDR_CONFIG; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.sdram_cfg = CFG_DDR_CONTROL; - - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.csbnds[1].csbnds = + (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >> + CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG; + + im->ddr.cs_config[2] = 0; + im->ddr.cs_config[3] = 0; + + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL; + + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; #endif udelay(200); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; return msize; } -#endif /*!CFG_SPD_EEPROM */ +#endif /*!CONFIG_SYS_SPD_EEPROM */ int checkboard(void) { @@ -228,34 +292,56 @@ int checkboard(void) /* * if MPC8360EMDS is soldered with SDRAM */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) +#ifdef CONFIG_SYS_LB_SDRAM /* * Initialize SDRAM memory on the Local Bus. */ -void sdram_init(void) +static int sdram_init(unsigned int base) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbc = &immap->lbus; - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + fsl_lbc_t *lbc = LBC_BASE_ADDR; + const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; + int rem = base % sdram_size; + uint *sdram_addr; + + /* window base address should be aligned to the window size */ + if (rem) + base = base - rem + sdram_size; + + /* + * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB + * After relocated to DDR, reuse BAT5 for PCI MEM space + */ + if (base > CONFIG_MAX_MEM_MAPPED) { + unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; + unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; + + /* Setup the BAT6 for SDRAM */ + write_bat(DBAT6, batu, batl); + write_bat(IBAT6, batu, batl); + } + sdram_addr = (uint *)base; /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c + * Setup SDRAM Base and Option Registers */ + set_lbc_br(2, base | CONFIG_SYS_BR2); + set_lbc_or(2, CONFIG_SYS_OR2); + immap->sysconf.lblaw[2].bar = base; + immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2; + /*setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */ - lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */ asm("sync"); *sdram_addr = 0xff; udelay(100); @@ -263,7 +349,7 @@ void sdram_init(void) /* * We need do 8 times auto refresh operation. */ - lbc->lsdmr = CFG_LBC_LSDMR_2; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); *sdram_addr = 0xff; /* 1 times */ udelay(100); @@ -283,39 +369,83 @@ void sdram_init(void) udelay(100); /* Mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); *(sdram_addr + 0xcc) = 0xff; udelay(100); /* Normal operation */ - lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000; asm("sync"); *sdram_addr = 0xff; udelay(100); + + /* + * In non-aligned case we don't [normally] use that memory because + * there is a hole. + */ + if (rem) + return 0; + return CONFIG_SYS_LBC_SDRAM_SIZE; } #else -void sdram_init(void) -{ -} +static int sdram_init(unsigned int base) { return 0; } #endif #if defined(CONFIG_OF_BOARD_SETUP) +static void ft_board_fixup_qe_usb(void *blob, bd_t *bd) +{ + if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) + return; + + do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode", + "peripheral", sizeof("peripheral"), 1); +} + void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + ft_board_fixup_qe_usb(blob, bd); + /* + * mpc8360ea pb mds errata 2: RGMII timing + * if on mpc8360ea rev. 2.1, + * change both ucc phy-connection-types from rgmii-id to rgmii-rxid + */ + if (board_handle_erratum2()) { + int nodeoffset; + const char *prop; + int path; + + nodeoffset = fdt_path_offset(blob, "/aliases"); + if (nodeoffset >= 0) { +#if defined(CONFIG_HAS_ETH0) + /* fixup UCC 1 if using rgmii-id mode */ + prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); + if (prop) { + path = fdt_path_offset(blob, prop); + prop = fdt_getprop(blob, path, + "phy-connection-type", 0); + if (prop && (strcmp(prop, "rgmii-id") == 0)) + fdt_fixup_phy_connection(blob, path, + PHY_INTERFACE_MODE_RGMII_RXID); + } +#endif +#if defined(CONFIG_HAS_ETH1) + /* fixup UCC 2 if using rgmii-id mode */ + prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); + if (prop) { + path = fdt_path_offset(blob, prop); + prop = fdt_getprop(blob, path, + "phy-connection-type", 0); + if (prop && (strcmp(prop, "rgmii-id") == 0)) + fdt_fixup_phy_connection(blob, path, + PHY_INTERFACE_MODE_RGMII_RXID); + } +#endif + } + } } #endif