X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8544ds%2Fmpc8544ds.c;h=66fb228a908943fced11e9d2178e4d112658ca8b;hb=b6c180928c3c7c9efbdc5eb1b468c450c877abdf;hp=0be2d892d30b0793cb3f81d5b05ed117e39d69bf;hpb=797131c12595b3d0e2964b706006938c822ee874;p=u-boot diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 0be2d892d3..66fb228a90 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -1,23 +1,7 @@ /* - * Copyright 2007,2009 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -27,11 +11,13 @@ #include #include #include -#include +#include +#include #include #include #include #include +#include #include #include @@ -40,7 +26,7 @@ int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); u8 vboot; u8 *pixis_base = (u8 *)PIXIS_BASE; @@ -67,35 +53,10 @@ int checkboard (void) return 0; } -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - #ifdef CONFIG_PCIE3 static struct pci_controller pcie3_hose; #endif @@ -103,11 +64,10 @@ static struct pci_controller pcie3_hose; void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[4]; + struct fsl_pci_info pci_info; u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; - int num = 0; int pcie_ep, pcie_configured; @@ -118,21 +78,18 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - if (io_sel & 1) { - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) - printf (" eTSEC1 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf (" eTSEC3 is in sgmii mode.\n"); - } puts("\n"); #ifdef CONFIG_PCIE3 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ - SET_STD_PCIE_INFO(pci_info[num], 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); -#ifdef CONFIG_SYS_PCIE3_MEM_BUS2 + /* contains both PCIE3 MEM & IO space */ + set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, + LAW_TRGT_IF_PCIE_3); + SET_STD_PCIE_INFO(pci_info, 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs); + /* outbound memory */ pci_set_region(&pcie3_hose.regions[0], CONFIG_SYS_PCIE3_MEM_BUS2, @@ -141,11 +98,11 @@ void pci_init_board(void) PCI_REGION_MEM); pcie3_hose.region_count = 1; -#endif - printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + + printf("PCIE3: connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info.regs); + first_free_busno = fsl_pci_init_port(&pci_info, &pcie3_hose, first_free_busno); /* @@ -154,7 +111,7 @@ void pci_init_board(void) */ in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); } else { - printf (" PCIE3: disabled\n"); + printf("PCIE3: disabled\n"); } puts("\n"); #else @@ -162,64 +119,17 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); -#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 - /* outbound memory */ - pci_set_region(&pcie1_hose.regions[0], - CONFIG_SYS_PCIE1_MEM_BUS2, - CONFIG_SYS_PCIE1_MEM_PHYS2, - CONFIG_SYS_PCIE1_MEM_SIZE2, - PCI_REGION_MEM); - - pcie1_hose.region_count = 1; -#endif - printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf (" PCIE1: disabled\n"); - } - - puts("\n"); + SET_STD_PCIE_INFO(pci_info, 1); + first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info); #else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ + setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ #endif #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); -#ifdef CONFIG_SYS_PCIE2_MEM_BUS2 - /* outbound memory */ - pci_set_region(&pcie2_hose.regions[0], - CONFIG_SYS_PCIE2_MEM_BUS2, - CONFIG_SYS_PCIE2_MEM_PHYS2, - CONFIG_SYS_PCIE2_MEM_SIZE2, - PCI_REGION_MEM); - - pcie2_hose.region_count = 1; -#endif - printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf (" PCIE2: disabled\n"); - } - - puts("\n"); + SET_STD_PCIE_INFO(pci_info, 2); + first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info); #else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ + setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCI1 @@ -229,21 +139,26 @@ void pci_init_board(void) pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info[num], 1); - pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); + printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - pci_info[num].regs); + pci_info.regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf("PCI: disabled\n"); } puts("\n"); @@ -252,7 +167,6 @@ void pci_init_board(void) #endif } - int last_stage_init(void) { return 0; @@ -319,24 +233,54 @@ get_board_sys_clk(ulong dummy) return val; } + +#define MIIM_CIS8204_SLED_CON 0x1b +#define MIIM_CIS8204_SLEDCON_INIT 0x1115 +/* + * Hack to write all 4 PHYs with the LED values + */ +int board_phy_config(struct phy_device *phydev) +{ + static int do_once; + uint phyid; + struct mii_dev *bus = phydev->bus; + + if (phydev->drv->config) + phydev->drv->config(phydev); + if (do_once) + return 0; + + for (phyid = 0; phyid < 4; phyid++) + bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON, + MIIM_CIS8204_SLEDCON_INIT); + + do_once = 1; + + return 0; +} + + int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET + struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[2]; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif @@ -346,9 +290,14 @@ int board_eth_init(bd_t *bis) return 0; } - if (io_sel & 1) + if (is_serdes_configured(SGMII_TSEC1) || + is_serdes_configured(SGMII_TSEC3)) { fsl_sgmii_riser_init(tsec_info, num); + } + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); #endif @@ -356,25 +305,16 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + FT_FSL_PCI_SETUP; -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); -#endif -#ifdef CONFIG_PCIE3 - ft_fsl_pci_setup(blob, "pci3", &pcie2_hose); -#endif #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + return 0; } #endif