X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8560ads%2Fmpc8560ads.c;h=a45a5583c9362ad3739bdd771f337ee458417a11;hb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;hp=37308189d20d6aa04caab70046e53dfced23019c;hpb=8ed44d91c8122d00368523b0b746691c895d3b3c;p=u-boot diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 37308189d2..a45a5583c9 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -5,23 +5,7 @@ * * (C) Copyright 2002 Scott McNutt * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ @@ -36,6 +20,7 @@ #include #include #include +#include #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -43,8 +28,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void); /* @@ -235,13 +218,13 @@ void reset_phy (void) #endif #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) /* reset PHY */ - miiphy_reset("FCC1 ETHERNET", 0x0); + miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, 0x02, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_MII */ } @@ -251,10 +234,10 @@ int checkboard (void) puts("Board: ADS\n"); #ifdef CONFIG_PCI - printf(" PCI1: 32 bit, %d MHz (compiled)\n", + printf("PCI1: 32 bit, %d MHz (compiled)\n", CONFIG_SYS_CLK_FREQ / 1000000); #else - printf(" PCI1: disabled\n"); + printf("PCI1: disabled\n"); #endif /* @@ -265,54 +248,6 @@ int checkboard (void) return 0; } - -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * Initialize SDRAM. - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -321,7 +256,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -337,14 +272,14 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ } else { /* @@ -359,7 +294,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */ udelay(200); /* @@ -376,21 +311,20 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ - -void -sdram_init(void) +void lbc_sdram_init(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - puts(" SDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + puts("LBC SDRAM: "); + print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + "\n "); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); @@ -436,10 +370,10 @@ sdram_init(void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;