X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8568mds%2Fbcsr.h;h=046025bbb2981b4c5033ea74340f2c61cfaac97e;hb=5f91ef6acdbadec33e0192049e2b24a1d9692f1d;hp=aefd9bf54d388b94d869b71f1839f27b8c8419d2;hpb=feaa43f3a8f465cbf01ffa1b23b6b52431819a52;p=u-boot

diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h
index aefd9bf54d..046025bbb2 100644
--- a/board/freescale/mpc8568mds/bcsr.h
+++ b/board/freescale/mpc8568mds/bcsr.h
@@ -32,8 +32,8 @@
 	7	cfg boot seq
 
 	* BCSR 1 *
-	0:2 	cfg rom lock
-	3:5 	cfg host agent
+	0:2	cfg rom lock
+	3:5	cfg host agent
 	6	PCI IO
 	7	cfg RIO size
 
@@ -46,7 +46,7 @@
 	0	TSEC1 reduce
 	1	TSEC2 reduce
 	2:3	TSEC1 protocol
-	4:5 	TSEC2 protocol
+	4:5	TSEC2 protocol
 	6	PHY1 slave
 	7	PHY2 slave
 
@@ -70,9 +70,9 @@
 	7	Power on reset
 
 	* BCSR 7 *
-	2 	board host mode indication
-	5 	enable TSEC1 PHY
-	6 	enable TSEC2 PHY
+	2	board host mode indication
+	5	enable TSEC1 PHY
+	6	enable TSEC2 PHY
 
 	* BCSR 8 *
 	0	UCC GETH1 enable
@@ -90,6 +90,11 @@
 	7	Flash write protect
 */
 
+#define BCSR_UCC1_GETH_EN	(0x1 << 7)
+#define BCSR_UCC2_GETH_EN	(0x1 << 7)
+#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
+#define BCSR_UCC2_MODE_MSK	(0x3 << 0)
+
 /*BCSR Utils functions*/
 
 void enable_8568mds_duart(void);
@@ -97,4 +102,8 @@ void enable_8568mds_flash_write(void);
 void disable_8568mds_flash_write(void);
 void enable_8568mds_qe_mdio(void);
 
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void);
+#endif
+
 #endif	/* __BCSR_H_ */