X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8568mds%2Fmpc8568mds.c;h=bd859e4ee4bcbf2ae32ff9290e445ca59a1ac6bf;hb=6d8d4ef994a7c46e34b5fe53b1af7aa4f78192bf;hp=4568aa1df59ba55b49c60b4d50439c9c988f9814;hpb=334fb53514f7fa5e84ac09cc4636b468aa7ba41c;p=u-boot diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 4568aa1df5..bd859e4ee4 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor. + * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2002 Scott McNutt * @@ -25,8 +25,10 @@ #include #include #include +#include #include -#include +#include +#include #include #include #include @@ -97,11 +99,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - void local_bus_init(void); void sdram_init(void); @@ -121,10 +118,10 @@ int board_early_init_f (void) enable_8568mds_qe_mdio(); #endif -#ifdef CFG_I2C2_OFFSET +#ifdef CONFIG_SYS_I2C2_OFFSET /* Enable I2C2_SCL and I2C2_SDA */ volatile struct par_io *port_c; - port_c = (struct par_io*)(CFG_IMMR + 0xe0140); + port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); port_c->cpdir2 |= 0x0f000000; port_c->cppar2 &= ~0x0f000000; port_c->cppar2 |= 0x0a000000; @@ -140,7 +137,7 @@ int checkboard (void) return 0; } -long int +phys_size_t initdram(int board_type) { long dram_size = 0; @@ -156,21 +153,18 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); udelay(200); } #endif - dram_size = spd_sdram(); -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + /* * SDRAM Initialization */ @@ -186,15 +180,15 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; @@ -217,44 +211,41 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CFG_OR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); asm("msync"); - lbc->br2 = CFG_BR2_PRELIM; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lbcr = CFG_LBC_LBCR; - asm("msync"); - - - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); /* * MPC8568 uses "new" 15-16 style addressing. */ - lsdmr_common = CFG_LBC_LSDMR_COMMON; - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; + lsdmr_common |= LSDMR_BSMA1516; /* * Issue PRECHARGE ALL command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -264,7 +255,7 @@ sdram_init(void) * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -274,7 +265,7 @@ sdram_init(void) /* * Issue 8 MODE-set command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -283,7 +274,7 @@ sdram_init(void) /* * Issue NORMAL OP command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -292,45 +283,6 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - #if defined(CONFIG_PCI) #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc8568mds_config_table[] = { @@ -356,8 +308,6 @@ static struct pci_controller pci1_hose = { static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno = 0; - /* * pib_init() -- Initialize the PCA9555 IO expander on the PIB board */ @@ -401,163 +351,81 @@ pib_init(void) } #ifdef CONFIG_PCI -void -pci_init_board(void) +void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - -#ifdef CONFIG_PCI1 -{ - pib_init(); - - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); - struct pci_controller *hose = &pci1_hose; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; - uint pci_32 = 1; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + int pcie_ep, pcie_configured; - uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint pci_speed = 66666000; + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", +#ifdef CONFIG_PCI1 + pci_speed = 66666000; + pci_32 = 1; + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter" - ); - - /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - hose->first_busno = first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); - first_free_busno = hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); + pci_arb ? "arbiter" : "external-arbiter", + pci_info[num].regs); + + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); - - int pcie_configured = io_sel >= 1; - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); - printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); - - first_free_busno=hose->last_busno+1; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - printf (" PCIE: disabled\n"); + printf (" PCIE1: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } #endif /* CONFIG_PCI */ #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; - ft_cpu_setup(blob, bd); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif -#ifdef CONFIG_PCIE1 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } + FT_FSL_PCI_SETUP; } #endif