X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8569mds%2Fmpc8569mds.c;h=122490c026ed5d1bc4151f80e4ec22b23ec3aa1e;hb=8259e9c9adc263a3e9619bd4713dfddea19509b8;hp=56854caa8d4eaf56400d1b80e89c12adcdacc77d;hpb=02c631e6eec5439daea46f8cbdb1572b0df3c843;p=u-boot diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 56854caa8d..122490c026 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -1,35 +1,22 @@ /* - * Copyright 2009 Freescale Semiconductor. + * Copyright 2009-2010 Freescale Semiconductor. * * (C) Copyright 2002 Scott McNutt * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include #include +#include #include #include -#include +#include +#include #include #include #include @@ -37,10 +24,12 @@ #include #include #include +#include #include "bcsr.h" - -phys_size_t fixed_sdram(void); +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" +#endif const qe_iop_conf_t qe_iop_conf_tab[] = { /* QE_MUX_MDC */ @@ -208,51 +197,43 @@ int board_early_init_f (void) return 0; } -int checkboard (void) -{ - printf ("Board: 8569 MDS\n"); - - return 0; -} - -phys_size_t -initdram(int board_type) +int board_early_init_r(void) { - long dram_size = 0; + const unsigned int flashbase = CONFIG_SYS_NAND_BASE; + const u8 flash_esel = 0; - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 + * Remap Boot flash to caching-inhibited + * so that flash can be erased properly. */ - volatile ccsr_gur_t *gur = - (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - out_be32(&gur->ddrdllcr, 0x81000000); - udelay(200); -#endif + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; + set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, /* ts, esel */ + BOOKE_PAGESZ_64M, 1); /* tsize, iprot */ - puts(" DDR: "); - return dram_size; + return 0; +} + +int checkboard (void) +{ + printf ("Board: 8569 MDS\n"); + + return 0; } #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; uint d_init; out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); @@ -305,15 +286,13 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) @@ -524,52 +503,19 @@ static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd) clrbits_8(&bcsr[17], BCSR17_nUSBEN); } -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif /* CONFIG_PCIE1 */ - #ifdef CONFIG_PCI void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[1]; - u32 devdisr, pordevsr, io_sel; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - -#ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf (" PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ +#if defined(CONFIG_PQ_MDS_PIB) + pib_init(); #endif + fsl_pcie_init_board(0); } #endif /* CONFIG_PCI */ #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #if defined(CONFIG_SYS_UCC_RMII_MODE) int nodeoff, off, err; @@ -589,8 +535,9 @@ void ft_board_setup(void *blob, bd_t *bd) break; } - err = fdt_setprop_string(blob, nodeoff, "phy-connection-type", - "rmii"); + err = fdt_fixup_phy_connection(blob, nodeoff, + PHY_INTERFACE_MODE_RMII); + if (err < 0) { printf("WARNING: could not set phy-connection-type " "%s.\n", fdt_strerror(err)); @@ -628,11 +575,12 @@ void ft_board_setup(void *blob, bd_t *bd) #endif ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; + fdt_board_fixup_esdhc(blob, bd); fdt_board_fixup_qe_uart(blob, bd); fdt_board_fixup_qe_usb(blob, bd); + + return 0; } #endif