X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8569mds%2Ftlb.c;h=f852fc35c35fd1a4992811e53ed6b6eaac032c0c;hb=29840de6b6d322e9cca3d22d254a1d066afbef02;hp=73dcc3e66c5b4ebb484dfc09264b50cca4c7cd2b;hpb=08254a1a9795711a6e43ad6e73d88a3988706731;p=u-boot

diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index 73dcc3e66c..f852fc35c3 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* TLB 1 Initializations */
 	/*
-	 * TLBe 0:	64M	Non-cacheable, guarded
+	 * TLBe 0:	64M	write-through, guarded
 	 * Out of reset this entry is only 4K.
-	 * 0xfc000000	256K	NAND FLASH (CS3)
-	 * 0xfe000000	32M	NOR FLASH (CS0)
+	 * 0xfc000000	32MB	NAND FLASH (CS3)
+	 * 0xfe000000	32MB	NOR FLASH (CS0)
 	 */
+#ifdef CONFIG_NAND_SPL
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_64M, 1),
-
+#endif
 	/*
 	 * TLBe 1:	256KB	Non-cacheable, guarded
 	 * 0xf8000000	32K	BCSR