X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8572ds%2Fmpc8572ds.c;h=1bbf83214873d35a41974dddca61f6c9d8de3181;hb=92f7fed4f738149121c779fe1dda857585bdeccf;hp=933dd127ec922d68b0a008cfaf3f25183a795c50;hpb=a9e9d69dd8849aa230fab88a7f3f4435713763af;p=u-boot diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 933dd127ec..1bbf832148 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -1,23 +1,7 @@ /* - * Copyright 2007-2008 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -28,29 +12,24 @@ #include #include #include -#include +#include #include +#include #include #include #include #include +#include #include -#include "../common/pixis.h" #include "../common/sgmii_riser.h" -long int fixed_sdram(void); - int checkboard (void) { u8 vboot; u8 *pixis_base = (u8 *)PIXIS_BASE; - puts ("Board: MPC8572DS "); -#ifdef CONFIG_PHYS_64BIT - puts ("(36-bit addrmap) "); -#endif - printf ("Sys ID: 0x%02x, " + printf("Board: MPC8572DS Sys ID: 0x%02x, " "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), in_8(pixis_base + PIXIS_PVER)); @@ -74,23 +53,6 @@ int checkboard (void) return 0; } -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} #if !defined(CONFIG_SPD_EEPROM) /* @@ -100,7 +62,7 @@ phys_size_t initdram(int board_type) phys_size_t fixed_sdram (void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + struct ccsr_ddr __iomem *ddr = &immap->im_ddr; uint d_init; ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; @@ -148,125 +110,41 @@ phys_size_t fixed_sdram (void) #endif -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - #ifdef CONFIG_PCI void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel, host_agent, temp32; - int first_free_busno = 0; - int num = 0; + struct pci_controller *hose; + + fsl_pcie_init_board(0); + + hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR)); + + if (hose) { + u32 temp32; + u8 uli_busno = hose->first_busno + 2; - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; - - debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); - - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) - printf (" eTSEC1 is in sgmii mode.\n"); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) - printf (" eTSEC2 is in sgmii mode.\n"); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf (" eTSEC3 is in sgmii mode.\n"); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) - printf (" eTSEC4 is in sgmii mode.\n"); - - puts("\n"); -#ifdef CONFIG_PCIE3 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ - SET_STD_PCIE_INFO(pci_info[num], 3); - printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie3_hose, first_free_busno); /* * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. * Device 1d has the first on-board memory BAR. */ - pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0), + pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0), PCI_BASE_ADDRESS_1, &temp32); + if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { - void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), + void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0), temp32, 4, 0); debug(" uli1572 read to %p\n", p); in_be32(p); } - } else { - printf (" PCIE3: disabled\n"); } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ - SET_STD_PCIE_INFO(pci_info[num], 2); - printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf (" PCIE2: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE1 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf (" PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif } #endif int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 2; + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -277,8 +155,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ @@ -287,178 +171,43 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_GET_CLK_FROM_ICS307 -/* decode S[0-2] to Output Divider (OD) */ -static unsigned char ics307_S_to_OD[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* Calculate frequency being generated by ICS307-02 clock chip based upon - * the control bytes being programmed into it. */ -/* XXX: This function should probably go into a common library */ -static unsigned long -ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) -{ - const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; - unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); - unsigned long RDW = cw2 & 0x7F; - unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; - unsigned long freq; - - /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ - - /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for cyrstal - */ - - /* Adding 1 to get a "nicely" rounded number, but this needs - * more tweaking to get a "properly" rounded number. */ - - freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); - - debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, - freq); - return freq; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VSYSCLK0), - in_8(pixis_base + PIXIS_VSYSCLK1), - in_8(pixis_base + PIXIS_VSYSCLK2) - ); -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VDDRCLK0), - in_8(pixis_base + PIXIS_VDDRCLK1), - in_8(pixis_base + PIXIS_VDDRCLK2) - ); -} -#else -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x38; - i >>= 3; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - return val; -} -#endif - #ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { + struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif #ifdef CONFIG_TSEC4 SET_STD_TSEC_INFO(tsec_info[num], 4); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + if (is_serdes_configured(SGMII_TSEC4)) { + puts("eTSEC4 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif @@ -472,6 +221,10 @@ int board_eth_init(bd_t *bis) fsl_sgmii_riser_init(tsec_info, num); #endif + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); @@ -491,26 +244,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); -#ifdef CONFIG_PCIE3 - ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; + #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif } #endif - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif