X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8641hpcn%2Fmpc8641hpcn.c;h=455569e422b1f702cd332b3bf5ebf4d6f2156003;hb=43b62393da6dfdd7f503d1b37344463a05ea47b5;hp=49718dac6cad05e9c491a5126ab0fa4e18305c3a;hpb=ea393eb1d6a786fc2e895f90abb5f7e7541aef45;p=u-boot diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 49718dac6c..455569e422 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -1,5 +1,5 @@ /* - * Copyright 2006, 2007 Freescale Semiconductor. + * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -24,32 +24,38 @@ #include #include #include -#include +#include #include +#include #include #include #include #include -#include "../common/pixis.h" - phys_size_t fixed_sdram(void); -int board_early_init_f(void) -{ - return 0; -} - int checkboard(void) { - printf ("Board: MPC8641HPCN, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", - in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), - in8(PIXIS_BASE + PIXIS_PVER)); + u8 vboot; + u8 *pixis_base = (u8 *)PIXIS_BASE; + + printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), + in_8(pixis_base + PIXIS_PVER)); + + vboot = in_8(pixis_base + PIXIS_VBOOT); + if (vboot & PIXIS_VBOOT_FMAP) + printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); + else + puts ("Promjet\n"); + +#ifdef CONFIG_PHYS_64BIT + printf (" 36-bit physical address map\n"); +#endif return 0; } - phys_size_t initdram(int board_type) { @@ -61,12 +67,9 @@ initdram(int board_type) dram_size = fixed_sdram(); #endif -#if defined(CONFIG_SYS_RAMBOOT) - puts(" DDR: "); - return dram_size; -#endif + setup_ddr_bat(dram_size); - puts(" DDR: "); + debug(" DDR: "); return dram_size; } @@ -88,7 +91,7 @@ fixed_sdram(void) ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; @@ -106,9 +109,9 @@ fixed_sdram(void) #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; #endif asm("sync; isync"); @@ -119,138 +122,22 @@ fixed_sdram(void) } #endif /* !defined(CONFIG_SPD_EEPROM) */ - -#if defined(CONFIG_PCI) -static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ - -int first_free_busno = 0; - -extern int fsl_pci_setup_inbound_windows(struct pci_region *r); -extern void fsl_pci_init(struct pci_controller *hose); - void pci_init_board(void) { -#ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) - >> MPC8641_PORDEVSR_IO_SEL_SHIFT; - -#ifdef DEBUG - uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) - >> MPC8641_PORBMSR_HA_SHIFT; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); -#endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - debug("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + fsl_pcie_init_board(0); +#ifdef CONFIG_PCIE1 /* * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT - + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); - - } else { - puts("PCI-EXPRESS 1: Disabled\n"); - } -} -#else - puts("PCI-EXPRESS1: Disabled\n"); -#endif /* CONFIG_PCI1 */ - -#ifdef CONFIG_PCI2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; - struct pci_controller *hose = &pci2_hose; - struct pci_region *r = hose->regions; - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BUS, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BUS, - CONFIG_SYS_PCI2_IO_PHYS, - CONFIG_SYS_PCI2_IO_SIZE, - PCI_REGION_IO); - - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); -} -#else - puts("PCI-EXPRESS 2: Disabled\n"); -#endif /* CONFIG_PCI2 */ - + in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT + + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); +#endif /* CONFIG_PCIE1 */ } #if defined(CONFIG_OF_BOARD_SETUP) -extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, - struct pci_controller *hose); - void ft_board_setup(void *blob, bd_t *bd) { @@ -260,12 +147,7 @@ ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCI2 - ft_fsl_pci_setup(blob, "pci1", &pci2_hose); -#endif + FT_FSL_PCI_SETUP; /* * Warn if it looks like the device tree doesn't match u-boot. @@ -303,11 +185,12 @@ get_board_sys_clk(ulong dummy) { u8 i, go_bit, rd_clks; ulong val = 0; + u8 *pixis_base = (u8 *)PIXIS_BASE; - go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit = in_8(pixis_base + PIXIS_VCTL); go_bit &= 0x01; - rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); rd_clks &= 0x1C; /* @@ -318,11 +201,11 @@ get_board_sys_clk(ulong dummy) if (go_bit) { if (rd_clks == 0x1c) - i = in8(PIXIS_BASE + PIXIS_AUX); + i = in_8(pixis_base + PIXIS_AUX); else - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); } else { - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); } i &= 0x07; @@ -366,7 +249,9 @@ int board_eth_init(bd_t *bis) void board_reset(void) { - out8(PIXIS_BASE + PIXIS_RST, 0); + u8 *pixis_base = (u8 *)PIXIS_BASE; + + out_8(pixis_base + PIXIS_RST, 0); while (1) ;