X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fp1022ds%2Fp1022ds.c;h=25fdc2a740c033f236825ac203f171f5b51c8bc9;hb=a42c87f9d831c4eb36104255766cc7897876867c;hp=8b78404b85d2ae04c5aa031decf4fd88288fb93b;hpb=880c80d004acdc7370ab892df51c37c0cf0ff86d;p=u-boot

diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 8b78404b85..25fdc2a740 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  *          Timur Tabi <timur@freescale.com>
  *
@@ -22,6 +22,7 @@
 #include <asm/io.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <fsl_mdio.h>
 #include <tsec.h>
 #include <asm/fsl_law.h>
 #include <netdev.h>
@@ -38,6 +39,10 @@ int board_early_init_f(void)
 
 	/* Set pmuxcr to allow both i2c1 and i2c2 */
 	setbits_be32(&gur->pmuxcr, 0x1000);
+#ifdef CONFIG_SYS_RAMBOOT
+	setbits_be32(&gur->pmuxcr,
+		in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+#endif
 
 	/* Read back the register to synchronize the write. */
 	in_be32(&gur->pmuxcr);
@@ -45,6 +50,9 @@ int board_early_init_f(void)
 	/* Set the pin muxing to enable ETSEC2. */
 	clrbits_be32(&gur->pmuxcr2, 0x001F8000);
 
+	/* Enable the SPI */
+	clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+
 	return 0;
 }
 
@@ -52,12 +60,8 @@ int checkboard(void)
 {
 	u8 sw;
 
-	puts("Board: P1022DS ");
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap) ");
-#endif
-
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+	printf("Board: P1022DS Sys ID: 0x%02x, "
+	       "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
 
 	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
@@ -279,6 +283,7 @@ int board_early_init_r(void)
  */
 int board_eth_init(bd_t *bis)
 {
+	struct fsl_pq_mdio_info mdio_info;
 	struct tsec_info_struct tsec_info[2];
 	unsigned int num = 0;
 
@@ -291,6 +296,10 @@ int board_eth_init(bd_t *bis)
 	num++;
 #endif
 
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
 	return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
 }
 
@@ -299,7 +308,8 @@ int board_eth_init(bd_t *bis)
  * ft_codec_setup - fix up the clock-frequency property of the codec node
  *
  * Update the clock-frequency property based on the value of the 'audclk'
- * hwconfig option.  If audclk is not specified, then default to 12.288MHz.
+ * hwconfig option.  If audclk is not specified, then don't write anything
+ * to the device tree, because it means that the codec clock is disabled.
  */
 static void ft_codec_setup(void *blob, const char *compatible)
 {
@@ -308,12 +318,15 @@ static void ft_codec_setup(void *blob, const char *compatible)
 	u32 freq;
 
 	audclk = hwconfig_arg("audclk", &arglen);
-	if (audclk && (strncmp(audclk, "11", 2) == 0))
-		freq = 11289600;
-	else
-		freq = 12288000;
+	if (audclk) {
+		if (strncmp(audclk, "11", 2) == 0)
+			freq = 11289600;
+		else
+			freq = 12288000;
 
-	do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+		do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
+				       freq, 1);
+	}
 }
 
 void ft_board_setup(void *blob, bd_t *bd)
@@ -328,6 +341,10 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
+#ifdef CONFIG_HAS_FSL_DR_USB
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
 	FT_FSL_PCI_SETUP;
 
 #ifdef CONFIG_FSL_SGMII_RISER