X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fp1_p2_rdb%2Fp1_p2_rdb.c;h=806d90e6e48a67799dd65995c591e224c735a079;hb=561e710a979c86a0c647dd70d143cafc123bcd64;hp=3af660e775306710682a233e20512160f858368a;hpb=02c631e6eec5439daea46f8cbdb1572b0df3c843;p=u-boot

diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 3af660e775..806d90e6e4 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,6 +26,7 @@
 #include <asm/mmu.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
 #include <asm/io.h>
 #include <miiphy.h>
 #include <libfdt.h>
@@ -33,6 +34,7 @@
 #include <tsec.h>
 #include <vsc7385.h>
 #include <netdev.h>
+#include <rtc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,6 +56,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define BOARDREV_MASK	0x10100000
 #define BOARDREV_B	0x10100000
 #define BOARDREV_C	0x00100000
+#define BOARDREV_D	0x00000000
 
 #define SYSCLK_66	66666666
 #define SYSCLK_50	50000000
@@ -64,7 +67,7 @@ unsigned long get_board_sys_clk(ulong dummy)
 	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 	u32 val_gpdat, sysclk_gpio, board_rev_gpio;
 
-	val_gpdat = pgpio->gpdat;
+	val_gpdat = in_be32(&pgpio->gpdat);
 	sysclk_gpio = val_gpdat & SYSCLK_MASK;
 	board_rev_gpio = val_gpdat & BOARDREV_MASK;
 	if (board_rev_gpio == BOARDREV_C) {
@@ -77,6 +80,11 @@ unsigned long get_board_sys_clk(ulong dummy)
 			return SYSCLK_66;
 		else
 			return SYSCLK_50;
+	} else if (board_rev_gpio == BOARDREV_D) {
+		if(sysclk_gpio == 0)
+			return SYSCLK_66;
+		else
+			return SYSCLK_100;
 	}
 	return 0;
 }
@@ -100,12 +108,14 @@ int checkboard (void)
 	char board_rev = 0;
 	struct cpu_type *cpu;
 
-	val_gpdat = pgpio->gpdat;
+	val_gpdat = in_be32(&pgpio->gpdat);
 	board_rev_gpio = val_gpdat & BOARDREV_MASK;
 	if (board_rev_gpio == BOARDREV_C)
 		board_rev = 'C';
 	else if (board_rev_gpio == BOARDREV_B)
 		board_rev = 'B';
+	else if (board_rev_gpio == BOARDREV_D)
+		board_rev = 'D';
 	else
 		panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
 
@@ -148,6 +158,7 @@ int board_early_init_r(void)
 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel, BOOKE_PAGESZ_16M, 1);
+	rtc_reset();
 	return 0;
 }
 
@@ -156,7 +167,6 @@ int board_early_init_r(void)
 int board_eth_init(bd_t *bis)
 {
 	struct tsec_info_struct tsec_info[4];
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int num = 0;
 	char *tmp;
 	unsigned int vscfw_addr;
@@ -171,8 +181,10 @@ int board_eth_init(bd_t *bis)
 #endif
 #ifdef CONFIG_TSEC3
 	SET_STD_TSEC_INFO(tsec_info[num], 3);
-	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+	if (is_serdes_configured(SGMII_TSEC3)) {
+		puts("eTSEC3 is in sgmii mode.\n");
 		tsec_info[num].flags |= TSEC_SGMII;
+	}
 	num++;
 #endif
 	if (!num) {
@@ -198,6 +210,8 @@ int board_eth_init(bd_t *bis)
 #endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_pci_board_setup(void *blob);
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
@@ -208,15 +222,10 @@ void ft_board_setup(void *blob, bd_t *bd)
 	base = getenv_bootm_low();
 	size = getenv_bootm_size();
 
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-}
-#endif
+#if defined(CONFIG_PCI)
+	ft_pci_board_setup(blob);
+#endif /* #if defined(CONFIG_PCI) */
 
-#ifdef CONFIG_MP
-extern void cpu_mp_lmb_reserve(struct lmb *lmb);
-
-void board_lmb_reserve(struct lmb *lmb)
-{
-	cpu_mp_lmb_reserve(lmb);
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
 }
 #endif