X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Fp2020ds%2Fp2020ds.c;h=608ff916da819f78236bed570c8572ba30bfd525;hb=1b43b5d7a637b3da97304724c9a7ddfd0d9c0f76;hp=7ad9be88c32976a4f78999084b6ffc69c215c629;hpb=3e7b6c1f2db5ec31f9e7dbc3e0cbca602167a46a;p=u-boot diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 7ad9be88c3..608ff916da 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -38,7 +38,7 @@ #include #include -#include "../common/pixis.h" +#include "../common/ngpixis.h" #include "../common/sgmii_riser.h" DECLARE_GLOBAL_DATA_PTR; @@ -47,41 +47,38 @@ phys_size_t fixed_sdram(void); int checkboard(void) { - u8 sw7; - u8 *pixis_base = (u8 *)PIXIS_BASE; + u8 sw; puts("Board: P2020DS "); #ifdef CONFIG_PHYS_64BIT puts("(36-bit addrmap) "); #endif - printf("Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - sw7 = in_8(pixis_base + PIXIS_SW(7)); - switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) { - case 0: - case 1: - printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4)); - break; - case 2: - case 3: - puts ("Promjet\n"); - break; - } + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); + + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); + sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + /* The lower two bits are the actual vbank number */ + printf("vBank: %d\n", sw & 3); + else + puts("Promjet\n"); return 0; } +const char *board_hwconfig = "foo:bar=baz"; +const char *cpu_hwconfig = "foo:bar=baz"; + phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; puts("Initializing...."); -#ifdef CONFIG_SPD_EEPROM +#ifdef CONFIG_DDR_SPD dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); @@ -100,7 +97,7 @@ phys_size_t initdram(int board_type) return dram_size; } -#if !defined(CONFIG_SPD_EEPROM) +#if !defined(CONFIG_DDR_SPD) /* * Fixed sdram init -- doesn't use serial presence detect. */ @@ -192,69 +189,40 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -int first_free_busno = 0; - #ifdef CONFIG_PCI void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel; + int first_free_busno = 0; + int num = 0; - volatile ccsr_fsl_pci_t *pci; - struct pci_controller *hose; int pcie_ep, pcie_configured; - struct pci_region *r; -/* u32 temp32; */ - debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf(" eTSEC2 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) printf(" eTSEC3 is in sgmii mode.\n"); + puts("\n"); #ifdef CONFIG_PCIE2 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - hose = &pcie2_hose; - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { - printf("\n PCIE2 connected to ULI as %s (base addr %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno = hose->last_busno+1; - printf(" PCIE2 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf(" PCIE2 connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); /* * The workaround doesn't work on p2020 because the location @@ -279,104 +247,47 @@ void pci_init_board(void) } else { printf(" PCIE2: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCIE3 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - hose = &pcie3_hose; - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { - printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BUS, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno+1; - printf(" PCIE3 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - + SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); + printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); } else { printf(" PCIE3: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE1 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - hose = &pcie1_hose; - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { - printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf(" PCIE1: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } #endif @@ -384,7 +295,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 2; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -405,165 +316,6 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_GET_CLK_FROM_ICS307 -/* decode S[0-2] to Output Divider (OD) */ -static unsigned char ics307_S_to_OD[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* Calculate frequency being generated by ICS307-02 clock chip based upon - * the control bytes being programmed into it. */ -/* XXX: This function should probably go into a common library */ -static unsigned long -ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2) -{ - const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; - unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); - unsigned long RDW = cw2 & 0x7F; - unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; - unsigned long freq; - - /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ - - /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for cyrstal - */ - - /* Adding 1 to get a "nicely" rounded number, but this needs - * more tweaking to get a "properly" rounded number. */ - - freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); - - debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, - freq); - return freq; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - return gd->bus_clk; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - return gd->mem_clk; -} - -unsigned long -calculate_board_sys_clk(ulong dummy) -{ - ulong val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - val = ics307_clk_freq( - in_8(pixis_base + PIXIS_VSYSCLK0), - in_8(pixis_base + PIXIS_VSYSCLK1), - in_8(pixis_base + PIXIS_VSYSCLK2)); - debug("sysclk val = %lu\n", val); - return val; -} - -unsigned long -calculate_board_ddr_clk(ulong dummy) -{ - ulong val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - val = ics307_clk_freq( - in_8(pixis_base + PIXIS_VDDRCLK0), - in_8(pixis_base + PIXIS_VDDRCLK1), - in_8(pixis_base + PIXIS_VDDRCLK2)); - debug("ddrclk val = %lu\n", val); - return val; -} -#else -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x38; - i >>= 3; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - return val; -} -#endif - #ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { @@ -617,15 +369,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); -#ifdef CONFIG_PCIE3 - ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; + #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif