X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ffreescale%2Ft104xrdb%2Ft104xrdb.c;h=322765288b0881303c84d9df7c590f525c74748f;hb=5076c64a08d2083af5a7761b12a30116ef0da967;hp=a5e5fffac4c8fc48da640d8a89b59d389acf234b;hpb=c9afa7cea84c9b7346fcd2710577bcc386631aba;p=u-boot

diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index a5e5fffac4..322765288b 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -6,19 +6,20 @@
 
 #include <common.h>
 #include <command.h>
+#include <hwconfig.h>
 #include <netdev.h>
 #include <linux/compiler.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_fdt.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
-#include <asm/mpc85xx_gpio.h>
-
+#include "../common/sleep.h"
 #include "t104xrdb.h"
 #include "cpld.h"
 
@@ -29,17 +30,28 @@ int checkboard(void)
 	struct cpu_type *cpu = gd->arch.cpu;
 	u8 sw;
 
+#ifdef CONFIG_T104XD4RDB
+	printf("Board: %sD4RDB\n", cpu->name);
+#else
 	printf("Board: %sRDB\n", cpu->name);
+#endif
 	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
 	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
 
 	sw = CPLD_READ(flash_ctl_status);
 	sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
 
-	if (sw <= 7)
-		printf("vBank: %d\n", sw);
-	else
-		printf("Unsupported Bank=%x\n", sw);
+	printf("vBank: %d\n", sw);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
 
 	return 0;
 }
@@ -48,7 +60,7 @@ int board_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FLASH_BASE
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
 	 * Remap Boot flash region to caching-inhibited
@@ -59,8 +71,14 @@ int board_early_init_r(void)
 	flush_dcache();
 	invalidate_icache();
 
-	/* invalidate existing TLB entry for flash */
-	disable_tlb(flash_esel);
+	if (flash_esel == -1) {
+		/* very unlikely unless something is messed up */
+		puts("Error: Could not find TLB for FLASH BASE\n");
+		flash_esel = 2;	/* give our best effort to continue */
+	} else {
+		/* invalidate existing TLB entry for flash */
+		disable_tlb(flash_esel);
+	}
 
 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -76,10 +94,44 @@ int board_early_init_r(void)
 
 int misc_init_r(void)
 {
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
+
+	printf("SERDES Reference : 0x%X\n", srds_s1);
+
+	/* select SGMII*/
+	if (srds_s1 == 0x86)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL);
+
+	/* select SGMII and Aurora*/
+	if (srds_s1 == 0x8E)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
+
+#if defined(CONFIG_T1040D4RDB)
+	if (hwconfig("qe-tdm")) {
+		CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
+			   MISC_MUX_QE_TDM);
+		printf("QECSR : 0x%02x, mux to qe-tdm\n",
+		       CPLD_READ(sfp_ctl_status));
+	}
+	/* Mask all CPLD interrupt sources, except QSGMII interrupts */
+	if (CPLD_READ(sw_ver) < 0x03) {
+		debug("CPLD SW version 0x%02x doesn't support int_mask\n",
+		      CPLD_READ(sw_ver));
+	} else {
+		CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
+			   ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
+	}
+#endif
+
 	return 0;
 }
 
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
 	phys_size_t size;
@@ -104,15 +156,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
 #endif
-}
 
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-	/* does not provide HW signals for power management */
-	CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
+	if (hwconfig("qe-tdm"))
+		fdt_del_diu(blob);
+	return 0;
 }
-#endif