X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fgdsys%2Fintip%2Finit.S;h=7513f1d3c3243a93f9767135e87c420f9b0ed91e;hb=e69e482bbf16795539af112d6a21d4ddaee35105;hp=e205c9d7e8e21f1ccaf624a80de1e826f7ed99cd;hpb=041a6a0c2ea8cd4039c34c5eeaf54b188c89b892;p=u-boot

diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S
index e205c9d7e8..7513f1d3c3 100644
--- a/board/gdsys/intip/init.S
+++ b/board/gdsys/intip/init.S
@@ -25,9 +25,10 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
 
 /**************************************************************************
  * TLB TABLE
@@ -51,7 +52,7 @@ tlbtab:
 	 * enable SA_I
 	 */
 	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
-		4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+		4, AC_RWX | SA_G) /* TLB 0 */
 
 	/*
 	 * TLB entries for SDRAM are not needed on this platform.
@@ -62,36 +63,36 @@ tlbtab:
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
 	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
-		0, AC_R|AC_W|AC_X|SA_G)
+		0, AC_RWX | SA_G)
 #endif
 
 	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
-		AC_R|AC_W|SA_G|SA_I)
+		AC_RW | SA_IG)
 	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
-		AC_R|AC_W|SA_G|SA_I)
+		AC_RW | SA_IG)
 
 	/* TLB-entry for NVRAM */
 	tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
-		AC_R|AC_W|SA_G|SA_I)
+		AC_RW | SA_IG)
 
 	/* TLB-entry for UART */
 	tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
-		AC_R|AC_W|SA_G|SA_I)
+		AC_RW | SA_IG)
 
 	/* TLB-entry for IO */
 	tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
-		AC_R|AC_W|SA_G|SA_I)
+		AC_RW | SA_IG)
 
 	/* TLB-entry for OCM */
 	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
-		AC_R|AC_W|AC_X|SA_I)
+		AC_RWX | SA_I)
 
 	/* TLB-entry for Local Configuration registers => peripherals */
 	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
-		4, AC_R|AC_W|AC_X|SA_G|SA_I)
+		4, AC_RWX | SA_IG)
 
 	/* AHB: Internal USB Peripherals (USB, SATA) */
 	tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
-		AC_R|AC_W|AC_X|SA_G|SA_I)
+		AC_RWX | SA_IG)
 
 	tlbtab_end