X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fgth2%2Flowlevel_init.S;h=bc31c00531204a4807281b9b28aad53a8ff8ad5f;hb=0cf7d2440e1aa91ca65f1fc08ba309184d376da6;hp=62e36574d30b2197b421a4994b8251dabe975695;hpb=0c32d96ddd7309b86ff92dfc1f3694908f174cf6;p=u-boot

diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S
index 62e36574d3..bc31c00531 100644
--- a/board/gth2/lowlevel_init.S
+++ b/board/gth2/lowlevel_init.S
@@ -1,13 +1,12 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>
 
 #define CP0_Config0		$16
-#define MEM_1MS			((CFG_MHZ) * 1000)
+#define MEM_1MS			((CONFIG_SYS_MHZ) * 1000)
 #define GPIO_RJ1LY     (1<<22)
 #define GPIO_CFRESET   (1<<10)
 
@@ -197,11 +196,11 @@ noCacheJump:
 
 	/* RCE2 CP Altera */
 	li	t0, MEM_STCFG2
-	li	t1, 0x00000280 /* BE, EW */ 
+	li	t1, 0x00000280 /* BE, EW */
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STTIME2
-	li	t1, 0x0303000c 
+	li	t1, 0x0303000c
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STADDR2
@@ -210,11 +209,11 @@ noCacheJump:
 
 	/* RCE3 DP Altera */
 	li	t0, MEM_STCFG3
-	li	t1, 0x00000280 /* BE, EW */ 
+	li	t1, 0x00000280 /* BE, EW */
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STTIME3
-	li	t1, 0x0303000c 
+	li	t1, 0x0303000c
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STADDR3
@@ -413,7 +412,9 @@ noCacheJump:
 	j clearmem
 	nop
 
+#if 0
 	.globl	memtest
+#endif
 memtest:
 	/* Fill memory with address */
 	li	t0, 0x80000000
@@ -428,14 +429,16 @@ mt0:	sw	t0, 0(t0)
 	li	t0, 0x80000000
 	li	t1, 0xFFF000 /* 64 MB */
 mt1:	lw	t2, 0(t0)
-	bne	t0, t2, memhang	
+	bne	t0, t2, memhang
 	add	t1, -1
 	add	t0, 4
 	bne	t1, zero, mt1
 	nop
 	nop
+#if 0
 	.globl	clearmem
-clearmem:		
+#endif
+clearmem:
 		/* Clear memory */
 	li	t0, 0x80000000
 	li	t1, 0xFFF000 /* 64 MB */
@@ -445,10 +448,10 @@ mtc:	sw	zero, 0(t0)
 	bne	t1, zero, mtc
 	nop
 	nop
-memtestend:		
-	j	ra
+memtestend:
+	jr	ra
 	nop
-	
-memhang:	
+
+memhang:
 	b	memhang
 	nop