X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fhighbank%2Fhighbank.c;h=4b272c780e101477074a85bb317f8cfc0671fa08;hb=db6b5e8b028e1aab92bc2482b6e02c681819e7c9;hp=8cdcea8aaca54f548738bf7503245a6d51053c21;hpb=5b9c79a81db80c3f9e50c77477957cd803429af8;p=u-boot

diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 8cdcea8aac..4b272c780e 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -12,13 +12,21 @@
 #include <asm/sizes.h>
 #include <asm/io.h>
 
+#define HB_AHCI_BASE			0xffe08000
+
 #define HB_SREG_A9_PWR_REQ		0xfff3cf00
 #define HB_SREG_A9_BOOT_SRC_STAT	0xfff3cf04
+#define HB_SREG_A9_PWRDOM_STAT		0xfff3cf20
+
 #define HB_PWR_SUSPEND			0
 #define HB_PWR_SOFT_RESET		1
 #define HB_PWR_HARD_RESET		2
 #define HB_PWR_SHUTDOWN			3
 
+#define PWRDOM_STAT_SATA		0x80000000
+#define PWRDOM_STAT_PCI			0x40000000
+#define PWRDOM_STAT_EMMC		0x20000000
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -43,13 +51,17 @@ int board_eth_init(bd_t *bis)
 	return rc;
 }
 
+#ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {
 	char envbuffer[16];
 	u32 boot_choice;
+	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
 
-	ahci_init(0xffe08000);
-	scsi_scan(1);
+	if (reg & PWRDOM_STAT_SATA) {
+		ahci_init(HB_AHCI_BASE);
+		scsi_scan(1);
+	}
 
 	boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
 	sprintf(envbuffer, "bootcmd%d", boot_choice);
@@ -61,6 +73,7 @@ int misc_init_r(void)
 
 	return 0;
 }
+#endif
 
 int dram_init(void)
 {
@@ -74,6 +87,22 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[0].size =  PHYS_SDRAM_1_SIZE;
 }
 
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *fdt, bd_t *bd)
+{
+	static const char disabled[] = "disabled";
+	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
+
+	if (!(reg & PWRDOM_STAT_SATA))
+		do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
+			disabled, sizeof(disabled), 1);
+
+	if (!(reg & PWRDOM_STAT_EMMC))
+		do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
+			disabled, sizeof(disabled), 1);
+}
+#endif
+
 void reset_cpu(ulong addr)
 {
 	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);