X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ficecube%2Fflash.c;h=a044e8f24a9f016bb8bdde16cef6545d60035cf9;hb=ffe1691159bf0d075cd4eabae63384cbaf6475d9;hp=9164bd9ea16ed27b8ea38c09dd0fa1a92760580b;hpb=945af8d723a29e9b6289d84250745ed0dc16fc81;p=u-boot diff --git a/board/icecube/flash.c b/board/icecube/flash.c index 9164bd9ea1..a044e8f24a 100644 --- a/board/icecube/flash.c +++ b/board/icecube/flash.c @@ -2,28 +2,13 @@ * (C) Copyright 2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +#ifndef CONFIG_FLASH_CFI_DRIVER +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it * has nothing to do with the flash chip being 8-bit or 16-bit. @@ -64,42 +49,39 @@ unsigned long flash_init (void) unsigned long size = 0; int i; extern void flash_preinit(void); + extern void flash_afterinit(ulong); + ulong flashbase = CONFIG_SYS_FLASH_BASE; flash_preinit(); /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { - ulong flashbase = CFG_FLASH_BASE; - + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { memset(&flash_info[i], 0, sizeof(flash_info_t)); flash_info[i].size = flash_get_size((FPW *)flashbase, &flash_info[i]); - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - size += flash_info[i].size; + flashbase += 0x800000; } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + flash_get_info(CONFIG_ENV_ADDR)); #endif + flash_afterinit(size); return size ? size : 1; } @@ -124,13 +106,14 @@ static flash_info_t *flash_get_info(ulong base) int i; flash_info_t * info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { info = & flash_info[i]; - if (info->start[0] <= base && base <= info->start[0] + info->size - 1) + if (info->size && + info->start[0] <= base && base <= info->start[0] + info->size - 1) break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; } /*----------------------------------------------------------------------- @@ -141,7 +124,7 @@ void flash_print_info (flash_info_t *info) int i; uchar *boottype; uchar *bootletter; - uchar *fmt; + char *fmt; uchar botbootletter[] = "B"; uchar topbootletter[] = "T"; uchar botboottype[] = "bottom boot sector"; @@ -211,6 +194,8 @@ void flash_print_info (flash_info_t *info) ulong flash_get_size (FPWV *addr, flash_info_t *info) { int i; + FPWV* addr2; + /* Write auto select command: read Manufacturer ID */ /* Write auto select command sequence and test FLASH answer */ addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ @@ -256,6 +241,17 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info) return (0); /* => no or unknown flash */ } + /* test for real flash at bank 1 */ + addr2 = (FPW *)((ulong)addr | 0x800000); + if (addr2 != addr && + ((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) { + /* Seems 2 banks are the same space (8Mb chip is installed, + * J24 in default position (CS0)). Disable this (first) bank. + */ + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + } /* Put FLASH back in read mode */ flash_reset(info); @@ -348,7 +344,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -362,14 +358,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ putc ('.'); last = get_timer(0); } } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc ('.'); last = get_timer(0); } @@ -470,7 +466,7 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00F000F0; /* reset bank */ res = 1; } @@ -478,3 +474,4 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) return (res); } +#endif /*CONFIG_FLASH_CFI_DRIVER*/