X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fids8247%2Fids8247.c;h=02db07f1dbbf95367a39d26b7000dd58764515d3;hb=6b9408edd3f6af6e91bcc0eebd4aedc0aca28934;hp=7b9a83d0f954b195830391a02977ee2d3f78cecd;hpb=197b049b8b8a488384f351b988dd15f78830ba4e;p=u-boot diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index 7b9a83d0f9..02db07f1db 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -25,6 +25,12 @@ #include #include +#if defined(CONFIG_OF_LIBFDT) +#include +#include +#include +#endif + DECLARE_GLOBAL_DATA_PTR; /* @@ -38,12 +44,12 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port A configuration */ { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ #if defined(CONFIG_SOFT_I2C) /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ @@ -53,14 +59,14 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ #endif /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ @@ -79,20 +85,20 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port B configuration */ { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ @@ -123,8 +129,8 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ @@ -180,7 +186,7 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */ + /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ @@ -224,7 +230,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * mapped by the controller. That means, that the initial mapping has * to be (at least) twice as large as the maximum expected size. */ - maxsize = (1 + (~orx | 0x7fff)) / 2; + maxsize = (1 + (~orx | 0x7fff))/* / 2*/; sdmr_ptr = &memctl->memc_psdmr; orx_ptr = &memctl->memc_or2; @@ -248,7 +254,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -259,7 +265,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -270,25 +276,24 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - long psize, lsize; + long psize; psize = 16 * 1024 * 1024; - lsize = 0; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - psize = try_init (memctl, CFG_PSDMR, CFG_OR2, - (uchar *) CFG_SDRAM_BASE); -#endif /* CFG_RAMBOOT */ + psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2, + (uchar *) CONFIG_SYS_SDRAM_BASE); +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -298,21 +303,104 @@ long int initdram (int board_type) int misc_init_r (void) { gd->bd->bi_flashstart = 0xff800000; + return 0; } -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern ulong -nand_probe (ulong physadr); +#if defined(CONFIG_CMD_NAND) +#include +#include +#include + +static u8 hwctl; -void -nand_init (void) +static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - ulong totlen = 0; + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + if ( ctrl & NAND_CLE ) { + hwctl |= 0x1; + writeb(0x00, (this->IO_ADDR_W + 0x0a)); + } else { + hwctl &= ~0x1; + writeb(0x00, (this->IO_ADDR_W + 0x08)); + } + if ( ctrl & NAND_ALE ) { + hwctl |= 0x2; + writeb(0x00, (this->IO_ADDR_W + 0x09)); + } else { + hwctl &= ~0x2; + writeb(0x00, (this->IO_ADDR_W + 0x08)); + } + if ( (ctrl & NAND_NCE) != NAND_NCE) + writeb(0x00, (this->IO_ADDR_W + 0x0c)); + else + writeb(0x00, (this->IO_ADDR_W + 0x08)); + } + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); - debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); - totlen += nand_probe (CFG_NAND0_BASE); +} + +static u_char ids_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; - printf ("%4lu MB\n", totlen >>20); + return readb(this->IO_ADDR_R); } -#endif /* CFG_CMD_NAND */ +static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + struct nand_chip *nand = mtd->priv; + int i; + + for (i = 0; i < len; i++) { + if (hwctl & 0x1) + writeb(buf[i], (nand->IO_ADDR_W + 0x02)); + else if (hwctl & 0x2) + writeb(buf[i], (nand->IO_ADDR_W + 0x01)); + else + writeb(buf[i], nand->IO_ADDR_W); + } +} + +static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + int i; + + for (i = 0; i < len; i++) { + buf[i] = readb(this->IO_ADDR_R); + } +} + +static int ids_nand_dev_ready(struct mtd_info *mtd) +{ + /* constant delay (see also tR in the datasheet) */ + udelay(12); + return 1; +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; + + /* Reference hardware control function */ + nand->cmd_ctrl = ids_nand_hwctrl; + nand->read_byte = ids_nand_read_byte; + nand->write_buf = ids_nand_write_buf; + nand->read_buf = ids_nand_read_buf; + nand->dev_ready = ids_nand_dev_ready; + nand->chip_delay = 12; + + return 0; +} + +#endif /* CONFIG_CMD_NAND */ + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup( blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */