X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fincaip%2Fincaip.c;h=3b30970b93984fbf2622aa592de918692da12b09;hb=bd6ce9d171b45465daa23bede5214100dd8b5eba;hp=6fe852cf9ed0fdefc57e98f7e2107bfc1fd2a3c5;hpb=16116ddd0d0158f4e91c91dc979b845b6e98a99d;p=u-boot

diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index 6fe852cf9e..3b30970b93 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -40,16 +40,16 @@ static ulong max_sdram_size(void)
 {
 	/* The only supported SDRAM data width is 16bit.
 	 */
-#define CFG_DW	2
+#define CONFIG_SYS_DW	2
 
 	/* The only supported number of SDRAM banks is 4.
 	 */
-#define CFG_NB	4
+#define CONFIG_SYS_NB	4
 
 	ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
 	int   cols   = cfgpb0 & 0xF;
 	int   rows   = (cfgpb0 & 0xF0) >> 4;
-	ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
+	ulong size   = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB;
 
 	return size;
 }
@@ -75,7 +75,7 @@ phys_size_t initdram(int board_type)
 		{
 			*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
 			                           (rows << 4) | cols;
-			size = get_ram_size((long *)CFG_SDRAM_BASE,
+			size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 			                                     max_sdram_size());
 
 			if (size > max_size)