X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fincaip%2Fincaip.c;h=3b30970b93984fbf2622aa592de918692da12b09;hb=bd6ce9d171b45465daa23bede5214100dd8b5eba;hp=c624b3d82e236e5402ed3fb042ec44429108f599;hpb=6525489323e5ab88cda947b4bc5a228ee624a75c;p=u-boot diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index c624b3d82e..3b30970b93 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -39,21 +40,21 @@ static ulong max_sdram_size(void) { /* The only supported SDRAM data width is 16bit. */ -#define CFG_DW 2 +#define CONFIG_SYS_DW 2 /* The only supported number of SDRAM banks is 4. */ -#define CFG_NB 4 +#define CONFIG_SYS_NB 4 ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; int cols = cfgpb0 & 0xF; int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; + ulong size = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB; return size; } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0; ulong size, max_size = 0; @@ -63,7 +64,7 @@ long int initdram(int board_type) /* Can't probe for RAM size unless we are running from Flash. */ - if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) + if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) { return max_sdram_size(); } @@ -74,7 +75,7 @@ long int initdram(int board_type) { *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) | (rows << 4) | cols; - size = get_ram_size((long *)CFG_SDRAM_BASE, + size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, max_sdram_size()); if (size > max_size) @@ -116,3 +117,10 @@ int checkboard (void) return 0; } + +#if defined(CONFIG_INCA_IP_SWITCH) +int board_eth_init(bd_t *bis) +{ + return inca_switch_initialize(bis); +} +#endif