X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Finka4x0%2Fmt48lc16m16a2-75.h;h=15477259cae4ae1ef2b4eafb571a76d6eb67a43d;hb=530135dcacac278798346ad5825c03131ce51772;hp=13a97ac4624221f84f8ede97a0d6d9457977f1d1;hpb=138ff60c1e76fdf0fa77ee1ec7ef299f96330c59;p=u-boot

diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h
index 13a97ac462..15477259ca 100644
--- a/board/inka4x0/mt48lc16m16a2-75.h
+++ b/board/inka4x0/mt48lc16m16a2-75.h
@@ -21,27 +21,10 @@
  * MA 02111-1307 USA
  */
 
-#define SDRAM_DDR	1		/* is SDR */
+#define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
-/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
-/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
-/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
 #define SDRAM_CONFIG2	0x8AD70000
-/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif