X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fjse%2Fhost_bridge.c;h=363be97a59150571ceb00c67460b9a994e088d65;hb=1a1b7374b89a04737c76948b00207b56a1bb37b6;hp=d68744518a78b9f7c453c6c52f75fc43d413fd49;hpb=db01a2ea991b539ffbd36ab952fcf2e754789a83;p=u-boot

diff --git a/board/jse/host_bridge.c b/board/jse/host_bridge.c
index d68744518a..363be97a59 100644
--- a/board/jse/host_bridge.c
+++ b/board/jse/host_bridge.c
@@ -39,10 +39,11 @@ void host_bridge_init (void)
 	/* The bridge chip is at a fixed location. */
 	pci_dev_t dev = PCI_BDF (0, 10, 0);
 
-	int rc;
-	u32 val32;
-
-	rc = pci_read_config_dword (dev, 0, &val32);
+	/* Set PCI Class code --
+	   The primary side sees this class code at 0x08 in the
+	   primary config space. This must be something other then a
+	   bridge, or MS Windows starts doing weird stuff to me. */
+	pci_write_config_dword (dev, 0x48, 0x04800000);
 
 	/* Set subsystem ID --
 	   The primary side sees this value at 0x2c. We set it here so