X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fkeymile%2Fkm_arm%2Fkm_arm.c;h=079509c979d01e3e2996cd2c90336c8e180785dd;hb=f32c86493822174e27f4b3c7c9359094406afbd8;hp=b9448873c8c263d3f5cb157aaaca80d21a01f3f0;hpb=dfdb3d37dd0fa8bdabdf7b5ffb597af470e74621;p=u-boot diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index b9448873c8..079509c979 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -9,23 +9,7 @@ * (C) Copyright 2010 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -36,7 +20,7 @@ #include #include #include -#include +#include #include #include "../common/common.h" @@ -53,6 +37,27 @@ DECLARE_GLOBAL_DATA_PTR; #define REG_IRQ_CIRQ2 0x2d #define MASK_RBI_DEFECT_16 0x01 +/* + * PHY registers definitions + */ +#define PHY_MARVELL_OUI 0x5043 +#define PHY_MARVELL_88E1118_MODEL 0x0022 +#define PHY_MARVELL_88E1118R_MODEL 0x0024 + +#define PHY_MARVELL_PAGE_REG 0x0016 +#define PHY_MARVELL_DEFAULT_PAGE 0x0000 + +#define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003 +#define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010 + +#define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000 +#define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0) +#define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4) +#define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8) + +/* I/O pin to erase flash RGPP09 = MPP43 */ +#define KM_FLASH_ERASE_ENABLE 43 + /* Multi-Purpose Pins Functionality configuration */ static const u32 kwmpp_config[] = { MPP0_NF_IO2, @@ -62,8 +67,12 @@ static const u32 kwmpp_config[] = { MPP4_NF_IO6, MPP5_NF_IO7, MPP6_SYSRST_OUTn, +#if defined(KM_PCIE_RESET_MPP7) + MPP7_GPO, +#else MPP7_PEX_RST_OUTn, -#if defined(CONFIG_SOFT_I2C) +#endif +#if defined(CONFIG_SYS_I2C_SOFT) MPP8_GPIO, /* SDA */ MPP9_GPIO, /* SCL */ #endif @@ -114,11 +123,13 @@ static const u32 kwmpp_config[] = { 0 }; +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + #if defined(CONFIG_KM_MGCOGE3UN) /* * Wait for startup OK from mgcoge3ne */ -int startup_allowed(void) +static int startup_allowed(void) { unsigned char buf; @@ -180,7 +191,6 @@ static int initialize_unit_leds(void) return 0; } -#if defined(CONFIG_BOOTCOUNT_LIMIT) static void set_bootcount_addr(void) { uchar buf[32]; @@ -189,14 +199,15 @@ static void set_bootcount_addr(void) sprintf((char *)buf, "0x%x", bootcountaddr); setenv("bootcountaddr", (char *)buf); } -#endif int misc_init_r(void) { #if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; + u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); wait_for_ne = getenv("waitforne"); - if (wait_for_ne != NULL) { + + if ((wait_for_ne != NULL) && (dip_switch == 0)) { if (strcmp(wait_for_ne, "true") == 0) { int cnt = 0; int abort = 0; @@ -224,25 +235,25 @@ int misc_init_r(void) } #endif + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + initialize_unit_leds(); set_km_env(); -#if defined(CONFIG_BOOTCOUNT_LIMIT) set_bootcount_addr(); -#endif return 0; } int board_early_init_f(void) { -#if defined(CONFIG_SOFT_I2C) +#if defined(CONFIG_SYS_I2C_SOFT) u32 tmp; /* set the 2 bitbang i2c pins as output gpios */ - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); + tmp = readl(MVEBU_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); #endif /* adjust SDRAM size for bank 0 */ - kw_sdram_size_adjust(0); + mvebu_sdram_size_adjust(0); kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -250,7 +261,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; /* * The KM_FLASH_GPIO_PIN switches between using a @@ -260,7 +271,7 @@ int board_init(void) kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); -#if defined(CONFIG_SOFT_I2C) +#if defined(CONFIG_SYS_I2C_SOFT) /* * Reinit the GPIO for I2C Bitbang driver so that the now * available gpio framework is consistent. The calls to @@ -285,9 +296,7 @@ int board_init(void) int board_late_init(void) { -#if defined(CONFIG_KMCOGE5UN) -/* I/O pin to erase flash RGPP09 = MPP43 */ -#define KM_FLASH_ERASE_ENABLE 43 +#if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN)) u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); /* if pin 1 do full erase */ @@ -338,15 +347,15 @@ void reset_phy(void) return; /* RGMII clk transition on data stable */ - if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) + if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) printf("Error reading PHY spec ctrl reg\n"); - if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf("Error writing PHY spec ctrl reg\n"); /* leds setup */ - if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf("Error writing PHY LED reg\n"); /* reset the phy */ @@ -359,7 +368,7 @@ void reset_phy(void) #if defined(CONFIG_KM_NUSA) struct mv88e_sw_reg extsw_conf[] = { /* - * port 0, PIGGY4, autoneg + * port 0, PIGGY4, autoneg * first the fix for the 1000Mbits Autoneg, this is from * a Marvell errata, the regs are undocumented */ @@ -421,6 +430,9 @@ void reset_phy(void) /* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) { + unsigned int oui; + unsigned char model, rev; + char *name = "egiga0"; if (miiphy_set_current_dev(name)) @@ -428,6 +440,40 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); + + /* get PHY model */ + if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev)) + return; + + /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */ + if ((oui == PHY_MARVELL_OUI) && + (model == PHY_MARVELL_88E1118R_MODEL)) { + /* set page register to 3 */ + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, + PHY_MARVELL_PAGE_REG, + PHY_MARVELL_88E1118R_LED_CTRL_PAGE)) + printf("Error writing PHY page reg\n"); + + /* + * leds setup as printed on PCB: + * LED2 (Link): 0x0 (On Link, Off No Link) + * LED1 (Activity): 0x3 (On Activity, Off No Activity) + * LED0 (Speed): 0x7 (On 1000 MBits, Off Else) + */ + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, + PHY_MARVELL_88E1118R_LED_CTRL_REG, + PHY_MARVELL_88E1118R_LED_CTRL_RESERVED | + PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB | + PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT | + PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK)) + printf("Error writing PHY LED reg\n"); + + /* set page register back to 0 */ + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, + PHY_MARVELL_PAGE_REG, + PHY_MARVELL_DEFAULT_PAGE)) + printf("Error writing PHY page reg\n"); + } } #endif @@ -435,12 +481,12 @@ void reset_phy(void) #if defined(CONFIG_HUSH_INIT_VAR) int hush_init_var(void) { - ivm_read_eeprom(); + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); return 0; } #endif -#if defined(CONFIG_SOFT_I2C) +#if defined(CONFIG_SYS_I2C_SOFT) void set_sda(int state) { I2C_ACTIVE;