X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fkorat%2Finit.S;h=3741277f60a0f64a1f6a87cdd43c7a1ef713e168;hb=0208aaf6c2e0f346e8410c0e5adb0ea784f00829;hp=ea43a1f89865611c7dc2e53c702ec905cfddfec7;hpb=6d0f6bcf337c5261c08fabe12982178c2c489d76;p=u-boot

diff --git a/board/korat/init.S b/board/korat/init.S
index ea43a1f898..3741277f60 100644
--- a/board/korat/init.S
+++ b/board/korat/init.S
@@ -19,8 +19,9 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
 #include <config.h>
 
 /**************************************************************************
@@ -43,7 +44,7 @@ tlbtab:
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-	tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
 
 	/*
 	 * TLB entries for SDRAM are not needed on this platform.  They are
@@ -53,37 +54,37 @@ tlbtab:
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
 	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
-		  AC_R|AC_W|AC_X|SA_G )
+		  AC_RWX | SA_G )
 #endif
 
 	/* TLB-entry for PCI Memory */
 	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
-		  CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
+		  CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
 
 	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
-		  CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
+		  CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
 
 	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
-		  CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
+		  CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
 
 	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
-		  CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
+		  CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
 
 	/* TLB-entry for EBC */
-	tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
 
 	/* TLB-entry for Internal Registers & OCM */
 	/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
-	tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
+	tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
 
 	/*TLB-entry PCI registers*/
-	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
 
 	/* TLB-entry for peripherals */
-	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
 
 	/* TLB-entry PCI IO Space - from sr@denx.de */
-	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
 
 	tlbtab_end