X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fmcc200%2Fmcc200.c;h=af047e2a0772a281303f99590ddc79fe1739bc12;hb=cfc67116a706fd18b8f6a9c11a16753c5626d689;hp=47073907e178f8a5dbf2c9a83e90665e66e5ef37;hpb=58ad4978330aefd6bdce72906f809bcfb6c94710;p=u-boot

diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 47073907e1..af047e2a07 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -27,18 +27,26 @@
 #include <common.h>
 #include <mpc5xxx.h>
 #include <pci.h>
+#include <asm/processor.h>
 
-//###CHD: es gibt eigentlich kein DDR bei uns -> weg damit!; dto. PCI!
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
+/* Two MT48LC8M32B2 for 32 MB */
+/* #include "mt48lc8m32b2-6-7.h" */
+
+/* One MT48LC16M32S2 for 64 MB */
+/* #include "mt48lc16m32s2-75.h" */
+#if defined (CONFIG_MCC200_SDRAM)
+#include "mt48lc16m16a2-75.h"
 #else
-//#include "mt48lc16m16a2-75.h"
-#include "mt48lc8m32b2-6-7.h"
+#include "mt46v16m16-75.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern flash_info_t flash_info[];	/* FLASH chips info */
 
-//###CHD: wenn RAMBOOT gehen wuerde, ....
+extern int do_auto_update(void);
+ulong flash_get_size (ulong base, int banknum);
+
 #ifndef CFG_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -77,20 +85,22 @@ static void sdram_start (int hi_addr)
 	/* normal operation */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 	__asm__ volatile ("sync");
+
+	udelay(10);
 }
 #endif
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
- *            is something else than 0x00000000.
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 long int initdram (int board_type)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
+	uint svr, pvr;
 #ifndef CFG_RAMBOOT
 	ulong test1, test2;
 
@@ -185,70 +195,38 @@ long int initdram (int board_type)
 
 #endif /* CFG_RAMBOOT */
 
-	return dramsize + dramsize2;
-}
-
-//###CHD: sowas gibt es bei usn nicht!
-#elif defined(CONFIG_MGT5100)
-
-long int initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
 	}
 
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CFG_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CFG_RAMBOOT */
-
-	return dramsize;
+	return dramsize + dramsize2;
 }
 
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
+#if defined(CONFIG_PRS200)
+	puts ("Board: PRS200\n");
+#else
 	puts ("Board: MCC200\n");
+#endif
 	return 0;
 }
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
+	ulong flash_sup_end, snum;
 
 	/*
 	 * Adjust flash start and offset to detected values
@@ -296,6 +274,25 @@ int misc_init_r (void)
 			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 	}
 
+	if (gd->bd->bi_flashsize > (32 << 20)) {
+		/* Unprotect the upper bank of the Flash */
+		*(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
+		flash_protect (FLAG_PROTECT_CLEAR,
+			       flash_info[0].start[0] + flash_info[0].size / 2,
+			       (flash_info[0].start[0] - 1) + flash_info[0].size,
+			       &flash_info[0]);
+		*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
+		printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
+		flash_info[0].size = 32 << 20;
+		for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
+			flash_info[0].start[snum] < flash_sup_end;
+			snum++);
+		flash_info[0].sector_count = snum;
+	}
+
+#ifdef CONFIG_AUTO_UPDATE
+	do_auto_update();
+#endif
 	return (0);
 }