X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fmpl%2Fcommon%2Fflash.c;h=fd430083e2fd63ddb39e554dde17eb6bdd32427d;hb=5da048adf44bea5e3b94080d02903c2e3fe7aa4a;hp=99f97d77386c096c31534d66104fea332527048e;hpb=7205e4075d8b50e4dd89fe39ed03860b23cbb704;p=u-boot diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 99f97d7738..fd430083e2 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -36,6 +36,8 @@ */ #include + +#if !defined(CONFIG_PATI) #include #include #include "common_util.h" @@ -46,6 +48,9 @@ #include "../pip405/pip405.h" #endif #include <405gp_pci.h> +#else /* defined(CONFIG_PATI) */ +#include +#endif flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- @@ -56,22 +61,15 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt); - -#ifdef CONFIG_PIP405 -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned short -#endif - -#ifdef CONFIG_MIP405 #define ADDR0 0x5555 #define ADDR1 0x2aaa #define FLASH_WORD_SIZE unsigned short -#endif #define FALSE 0 #define TRUE 1 +#if !defined(CONFIG_PATI) + /*----------------------------------------------------------------------- * Some CS switching routines: * @@ -86,14 +84,14 @@ void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt); * The first thing we do is to map the Flash CS to the Flash area and * the MPS CS to the MPS area. Since the flash size is unknown at this * point, we use the max flash size and the lowest flash address as base. - * + * * After flash detection we adjust the size of the CS area accordingly. * The board_init_r will fill in wrong values in the board init structure, * but this will be fixed in the misc_init_r routine: * bd->bi_flashstart=0-flash_info[0].size * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN * bd->bi_flashoffset=0 - * + * */ int get_boot_mode(void) { @@ -151,12 +149,16 @@ void setup_cs_reloc(void) } } - +#endif /* #if !defined(CONFIG_PATI) */ unsigned long flash_init (void) { - unsigned long size_b0, size_b1,flashcr; - int mode, i; + unsigned long size_b0; + int i; + +#if !defined(CONFIG_PATI) + unsigned long size_b1,flashcr,size_reg; + int mode; extern char version_string; char *p=&version_string; @@ -170,6 +172,7 @@ unsigned long flash_init (void) else printf("(%s Boot) ",(mode & BOOT_MPS) ? "MPS" : "Flash"); +#endif /* #if !defined(CONFIG_PATI) */ /* Init: no FLASHes known */ for (i=0; i>20); + switch (size_reg) { + case 0: + case 1: i=0; break; /* <= 1MB */ + case 2: i=1; break; /* = 2MB */ + case 4: i=2; break; /* = 4MB */ + case 8: i=3; break; /* = 8MB */ + case 16: i=4; break; /* = 16MB */ + case 32: i=5; break; /* = 32MB */ + case 64: i=6; break; /* = 64MB */ + case 128: i=7; break; /*= 128MB */ + default: + printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg); + while(1); + } if(mode & BOOT_MPS) { /* flash is on CS1 */ mtdcr(ebccfga, pb1cr); @@ -203,7 +222,7 @@ unsigned long flash_init (void) /* we map the flash high in every case */ flashcr&=0x0001FFFF; /* mask out address bits */ flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ - flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */ + flashcr|= (i << 17); /* size addr */ mtdcr(ebccfga, pb1cr); mtdcr(ebccfgd, flashcr); } @@ -214,12 +233,12 @@ unsigned long flash_init (void) /* we map the flash high in every case */ flashcr&=0x0001FFFF; /* mask out address bits */ flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ - flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */ + flashcr|= (i << 17); /* size addr */ mtdcr(ebccfga, pb0cr); mtdcr(ebccfgd, flashcr); } #if 0 - /* enable this if you want to test if + /* enable this (PIP405/MIP405 only) if you want to test if the relocation has be done ok. This will disable both Chipselects */ mtdcr (ebccfga, pb0cr); @@ -236,6 +255,15 @@ unsigned long flash_init (void) } p++; } +#else /* #if !defined(CONFIG_PATI) */ +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif +#endif /* #if !defined(CONFIG_PATI) */ return (size_b0); } @@ -330,7 +358,7 @@ void flash_print_info (flash_info_t *info) /*----------------------------------------------------------------------- - + */ /* @@ -529,7 +557,7 @@ int wait_for_DQ7(flash_info_t *info, int sect) while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { printf ("Timeout\n"); - return -1; + return ERR_TIMOUT; } /* show that we're waiting */ if ((now - last) > 1000) { /* every second */ @@ -537,12 +565,12 @@ int wait_for_DQ7(flash_info_t *info, int sect) last = now; } } - return 0; + return ERR_OK; } int intel_wait_for_DQ7(flash_info_t *info, int sect) { - ulong start, now, last; + ulong start, now, last, status; volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); start = get_timer (0); @@ -550,7 +578,7 @@ int intel_wait_for_DQ7(flash_info_t *info, int sect) while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { printf ("Timeout\n"); - return -1; + return ERR_TIMOUT; } /* show that we're waiting */ if ((now - last) > 1000) { /* every second */ @@ -558,8 +586,11 @@ int intel_wait_for_DQ7(flash_info_t *info, int sect) last = now; } } - addr[0]=(FLASH_WORD_SIZE)0x00500050; - return 0; + status = addr[0] & (FLASH_WORD_SIZE)0x00280028; + /* clear status register */ + addr[0] = (FLASH_WORD_SIZE)0x00500050; + /* check status for block erase fail and VPP low */ + return (status == 0 ? ERR_OK : ERR_NOT_ERASED); } /*----------------------------------------------------------------------- @@ -570,7 +601,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); volatile FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; - int i; + int i, rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -620,7 +651,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ for (i=0; i<50; i++) udelay(1000); /* wait 1 ms */ - wait_for_DQ7(info, sect); + rcode |= wait_for_DQ7(info, sect); } else { if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ @@ -629,7 +660,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) intel_wait_for_DQ7(info, sect); addr2[0] = (FLASH_WORD_SIZE)0x00200020; /* sector erase */ addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */ - intel_wait_for_DQ7(info, sect); + rcode |= intel_wait_for_DQ7(info, sect); } else { addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; @@ -638,7 +669,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - wait_for_DQ7(info, sect); + rcode |= wait_for_DQ7(info, sect); } } l_sect = sect; @@ -674,8 +705,10 @@ DONE: addr = (FLASH_WORD_SIZE *)info->start[0]; addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - printf (" done\n"); - return 0; + if (!rcode) + printf (" done\n"); + + return rcode; }