X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fmpl%2Fmip405%2Fmip405.c;h=e93d99407c543625bcfc718fe0204805e2cef236;hb=a7d54346e025d91bb4413c61b5f5ec13ae2a6bfc;hp=d8279e81c988f2444f37b1215e5826cbcd2c6329;hpb=084f3ddac6ab624a4b1c7174b3cdf9cc25866217;p=u-boot

diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index d8279e81c9..e93d99407c 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -65,7 +65,8 @@
 #include <common.h>
 #include "mip405.h"
 #include <asm/processor.h>
-#include <4xx_i2c.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-i2c.h>
 #include <miiphy.h>
 #include "../common/common_util.h"
 #include <stdio_dev.h>
@@ -348,7 +349,7 @@ int init_sdram (void)
 	/* trc_clocks is sum of trp_clocks + tras_clocks */
 	trc_clocks = trp_clocks + tras_clocks;
 	/* get SDRAM timing register */
-	mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
 	sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
 	/* insert CASL value */
 	sdram_tim |= ((unsigned long) (cal_val)) << 23;
@@ -369,7 +370,7 @@ int init_sdram (void)
 	/* insert SZ value; */
 	tmp |= ((unsigned long) sdram_table[i].sz << 17);
 	/* get SDRAM bank 0 register */
-	mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 	sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
 	sdram_bank |= (baseaddr | tmp | 0x01);
 
@@ -380,7 +381,7 @@ int init_sdram (void)
 #endif
 
 	/* write SDRAM timing register */
-	mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
 	mtdcr (SDRAM0_CFGDATA, sdram_tim);
 
 #ifdef SDRAM_DEBUG
@@ -390,22 +391,22 @@ int init_sdram (void)
 #endif
 
 	/* write SDRAM bank 0 register */
-	mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 	mtdcr (SDRAM0_CFGDATA, sdram_bank);
 
 	if (get_bus_freq (tmp) > 110000000) {	/* > 110MHz */
 		/* get SDRAM refresh interval register */
-		mtdcr (SDRAM0_CFGADDR, mem_rtr);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
 		tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
 		tmp |= 0x07F00000;
 	} else {
 		/* get SDRAM refresh interval register */
-		mtdcr (SDRAM0_CFGADDR, mem_rtr);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
 		tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
 		tmp |= 0x05F00000;
 	}
 	/* write SDRAM refresh interval register */
-	mtdcr (SDRAM0_CFGADDR, mem_rtr);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
 	mtdcr (SDRAM0_CFGDATA, tmp);
 	/* enable ECC if used */
 #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
@@ -415,18 +416,18 @@ int init_sdram (void)
 #ifdef SDRAM_DEBUG
 		serial_puts ("disable ECC.. ");
 #endif
-		mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
 		tmp = mfdcr (SDRAM0_CFGDATA);
 		tmp &= 0xff0fffff;		/* disable all banks */
-		mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
 		/* set up SDRAM Controller with ECC enabled */
 #ifdef SDRAM_DEBUG
 		serial_puts ("setup SDRAM Controller.. ");
 #endif
 		mtdcr (SDRAM0_CFGDATA, tmp);
-		mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 		tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
-		mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 		mtdcr (SDRAM0_CFGDATA, tmp);
 		udelay (600);
 #ifdef SDRAM_DEBUG
@@ -447,7 +448,7 @@ int init_sdram (void)
 		serial_puts ("enable ECC\n");
 #endif
 		udelay (400);
-		mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
 		tmp = mfdcr (SDRAM0_CFGDATA);
 		tmp |= 0x00800000;		/* enable bank 0 */
 		mtdcr (SDRAM0_CFGDATA, tmp);
@@ -456,9 +457,9 @@ int init_sdram (void)
 #endif
 	{
 		/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
-		mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 		tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
-		mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 		mtdcr (SDRAM0_CFGDATA, tmp);
 		udelay (400);
 	}
@@ -489,13 +490,13 @@ int board_early_init_f (void)
    |       caused the interrupt.
    |
    +-------------------------------------------------------------------------*/
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical (for now) */
-	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical (for now) */
+	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 	return 0;
 }
 
@@ -589,7 +590,7 @@ int checkboard (void)
 
 	puts ("Board: ");
 	get_pcbrev_var(&bc,&var);
-	i = getenv_r ("serial#", (char *)s, 32);
+	i = getenv_f("serial#", (char *)s, 32);
 	if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
 		get_backup_values (b);
 		if (strncmp (b->signature, "MPL\0", 4) != 0) {
@@ -631,13 +632,13 @@ phys_size_t initdram (int board_type)
 	ds = 0;
 	/* since the DRAM controller is allready set up, calculate the size with the
 	   bank registers    */
-	mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 	bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
-	mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
 	bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
-	mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
 	bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
-	mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
 	bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
 	TotalSize = 0;
 	for (i = 0; i < 4; i++) {
@@ -648,7 +649,7 @@ phys_size_t initdram (int board_type)
 		} else
 			ds = 1;
 	}
-	mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
 	tmp = mfdcr (SDRAM0_CFGDATA);
 
 	if (!tmp)
@@ -706,18 +707,6 @@ void print_mip405_rev (void)
 }
 
 
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-	return 0;	/* No hotkeys supported */
-}
-#endif
-
-extern void mem_test_reloc(void);
 extern int mk_date (char *, struct rtc_time *);
 
 int last_stage_init (void)
@@ -725,7 +714,7 @@ int last_stage_init (void)
 	unsigned long stop;
 	struct rtc_time newtm;
 	char *s;
-	mem_test_reloc();
+
 	/* write correct LED configuration */
 	if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
 		printf ("Error writing to the PHY\n");