X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fmpl%2Fvcma9%2Fvcma9.c;h=9f259c220bfd218dd13e0078474b972e5fd2a6a2;hb=0c669fd17a9d8452f70369474925a91139e3005d;hp=978e6fdeff9d9dae12780f2308dab37ee12851bc;hpb=d9abba8254c3e6b9a1d5c2e52c2d8088bbeb520f;p=u-boot diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 978e6fdeff..9f259c220b 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -3,7 +3,7 @@ * Sysgo Real-Time Solutions, GmbH * Marius Groeger * - * (C) Copyright 2002 + * (C) Copyright 2002, 2010 * David Mueller, ELSOFT AG, * * See file CREDITS for list of people who contributed to this @@ -27,103 +27,51 @@ #include #include -#include -#include #include +#include +#include #include "vcma9.h" #include "../common/common_util.h" DECLARE_GLOBAL_DATA_PTR; -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - /* * Miscellaneous platform dependent initialisations */ -int board_init(void) +int board_early_init_f(void) { - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x002AAAAA; - gpio->gpbup = 0x000002BF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x000037F7; - gpio->gpfcon = 0x00000000; - gpio->gpfup = 0x00000000; - gpio->gpgcon = 0xFFEAFF5A; - gpio->gpgup = 0x0000F0DC; - gpio->gphcon = 0x0028AAAA; - gpio->gphup = 0x00000656; - - /* setup correct IRQ modes for NIC */ - /* rising edge mode */ - gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); - - /* select USB port 2 to be host or device (fix to host for now) */ - gpio->misccr |= 0x08; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); + + /* setup correct IRQ modes for NIC (rising edge mode) */ + writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); + + /* select USB port 2 to be host or device (setup as host for now) */ + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); - /* init serial */ - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; - serial_init(); - - /* arch number of VCMA9-Board */ - gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9; + return 0; +} +int board_init(void) +{ /* adress of boot parameters */ gd->bd->bi_boot_params = 0x30000100; @@ -133,114 +81,33 @@ int board_init(void) return 0; } -/* - * NAND flash initialization. - */ -#if defined(CONFIG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - - -static inline void NF_Init(void) -{ -#if 0 /* a little bit too optimistic */ -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void -nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - /* * Get some Board/PLD Info */ -static u8 Get_PLD_ID(void) -{ - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->ID); -} - -static u8 Get_PLD_BOARD(void) -{ - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->BOARD); -} - -static u8 Get_PLD_SDRAM(void) -{ - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->SDRAM); -} - -static u8 Get_PLD_Version(void) +static u8 get_pld_reg(enum vcma9_pld_regs reg) { - return((Get_PLD_ID() >> 4) & 0x0F); + return readb(VCMA9_PLD_BASE + reg); } -static u8 Get_PLD_Revision(void) +static u8 get_pld_version(void) { - return(Get_PLD_ID() & 0x0F); + return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; } -#if 0 /* not used */ -static int Get_Board_Config(void) +static u8 get_pld_revision(void) { - u8 config = Get_PLD_BOARD() & 0x03; - - if (config == 3) - return 1; - else - return 0; + return get_pld_reg(VCMA9_PLD_ID) & 0x0F; } -#endif -static uchar Get_Board_PCB(void) +static uchar get_board_pcb(void) { - return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); + return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; } -static u8 Get_SDRAM_ChipNr(void) +static u8 get_nr_chips(void) { - switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { + switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { case 0: return 4; case 1: return 1; case 2: return 2; @@ -248,9 +115,9 @@ static u8 Get_SDRAM_ChipNr(void) } } -static ulong Get_SDRAM_ChipSize(void) +static ulong get_chip_size(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return 16 * (1024*1024); case 1: return 32 * (1024*1024); case 2: return 8 * (1024*1024); @@ -258,9 +125,10 @@ static ulong Get_SDRAM_ChipSize(void) default: return 0; } } -static const char * Get_SDRAM_ChipGeom(void) + +static const char *get_chip_geom(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return "4Mx8x4"; case 1: return "8Mx8x4"; case 2: return "2Mx8x4"; @@ -269,23 +137,21 @@ static const char * Get_SDRAM_ChipGeom(void) } } -static void Show_VCMA9_Info(char *board_name, char *serial) +static void vcma9_show_info(char *board_name, char *serial) { printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); - printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); + board_name, serial, + get_board_pcb(), get_pld_version(), get_pld_revision()); + printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); } int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); - + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_chip_size() * get_nr_chips(); return 0; } -/* ------------------------------------------------------------------------- */ - /* * Check Board Identity: */ @@ -303,50 +169,35 @@ int checkboard(void) puts ("### No HW ID - assuming VCMA9"); } else { b->serial_name[5] = 0; - Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); + vcma9_show_info(b->serial_name, &b->serial_name[6]); } } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } - /*printf("\n");*/ - return(0); -} - -int last_stage_init(void) -{ - checkboard(); - stdio_print_current_devices(); - check_env(); return 0; } -/*************************************************************************** - * some helping routines - */ -#if !CONFIG_USB_KEYBOARD -int overwrite_console(void) +int board_late_init(void) { - /* return TRUE if console should be overwritten */ + /* + * check if environment is healthy, otherwise restore values + * from shadow copy + */ + check_env(); return 0; } -#endif -/************************************************************************ -* Print VCMA9 Info -************************************************************************/ -void print_vcma9_info(void) +void vcma9_print_info(void) { - char s[50]; - int i; + char *s = getenv("serial#"); - if ((i = getenv_f("serial#", s, 32)) < 0) { + if (!s) { puts ("### No HW ID - assuming VCMA9"); - printf("i %d", i*24); } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } } @@ -360,3 +211,15 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F400BB flash. + */ +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +}