X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fmpr2%2Flowlevel_init.S;h=5246b63365edbaef06e1ee51e545c29658e42e9e;hb=0cba6abbba5c0bd5c80e652c35d0bd74e644a49e;hp=187b5bbeba49ce692ad647ad9f28bfe0169df3f2;hpb=e4430779623af500de1cee7892c379f07ef59813;p=u-boot

diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S
index 187b5bbeba..5246b63365 100644
--- a/board/mpr2/lowlevel_init.S
+++ b/board/mpr2/lowlevel_init.S
@@ -7,21 +7,9 @@
  *
  * board/mpr2/lowlevel_init.S
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
+#include <asm/macro.h>
 
 	.global	lowlevel_init
 
@@ -33,59 +21,35 @@ lowlevel_init:
 /*
  * Set frequency multipliers and dividers in FRQCR.
  */
-	mov.l	WTCSR_A, r1
-	mov.l	WTCSR_D, r0
-	mov.w	r0, @r1
+	write16	WTCSR_A, WTCSR_D
 
-	mov.l	WTCNT_A, r1
-	mov.l	WTCNT_D, r0
-	mov.w	r0, @r1
+	write16	WTCNT_A, WTCNT_D
 
-	mov.l	FRQCR_A, r1
-	mov.l	FRQCR_D, r0
-	mov.w	r0, @r1
+	write16	FRQCR_A, FRQCR_D
 
 /*
  * Setup CS0 (Flash).
  */
-	mov.l	CS0BCR_A, r1
-	mov.l	CS0BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS0BCR_A, CS0BCR_D
 
-	mov.l	CS0WCR_A, r1
-	mov.l	CS0WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS0WCR_A, CS0WCR_D
 
 /*
  * Setup CS3 (SDRAM).
  */
-	mov.l	CS3BCR_A, r1
-	mov.l	CS3BCR_D, r0
-	mov.l	r0, @r1
+	write32	CS3BCR_A, CS3BCR_D
 
-	mov.l	CS3WCR_A, r1
-	mov.l	CS3WCR_D, r0
-	mov.l	r0, @r1
+	write32	CS3WCR_A, CS3WCR_D
 
-	mov.l	SDCR_A, r1
-	mov.l	SDCR_D1, r0
-	mov.l	r0, @r1
+	write32	SDCR_A, SDCR_D1
 
-	mov.l	RTCSR_A, r1
-	mov.l	RTCSR_D, r0
-	mov.l	r0, @r1
+	write32	RTCSR_A, RTCSR_D
 
-	mov.l	RTCNT_A, r1
-	mov.l	RTCNT_D, r0
-	mov.l	r0, @r1
+	write32	RTCNT_A, RTCNT_D
 
-	mov.l	RTCOR_A, r1
-	mov.l	RTCOR_D, r0
-	mov.l	r0, @r1
+	write32	RTCOR_A, RTCOR_D
 
-	mov.l	SDCR_A, r1
-	mov.l	SDCR_D2, r0
-	mov.l	r0, @r1
+	write32	SDCR_A, SDCR_D2
 
 	mov.l	SDMR3_A, r1
 	mov.l	SDMR3_D, r0
@@ -105,10 +69,10 @@ lowlevel_init:
 /*
  * PLL Settings
  */
-FRQCR_D:	.long	0x1103		/* I:B:P=8:4:2 */
-WTCNT_D:	.long	0x5A00		/* start counting at zero */
-WTCSR_D:	.long	0xA507		/* divide by 4096 */
-
+FRQCR_D:	.word	0x1103		/* I:B:P=8:4:2 */
+WTCNT_D:	.word	0x5A00		/* start counting at zero */
+WTCSR_D:	.word	0xA507		/* divide by 4096 */
+.align 2
 /*
  * Spansion S29GL256N11 @ 48 MHz
  */