X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fmvblue%2Fmvblue.c;h=69abb06251e4e4e6cb64a8f47ee3043c15b0a410;hb=710308ee185b3087e474fb9b205f47613c65dda4;hp=056fee78484c68fc482dbda7d723c3192cfdaa4a;hpb=8ca0b3f99c4fce7a599dcaf92ae095496dc8c8e0;p=u-boot

diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c
index 056fee7848..69abb06251 100644
--- a/board/mvblue/mvblue.c
+++ b/board/mvblue/mvblue.c
@@ -38,8 +38,8 @@ u32 get_BoardType ()
 
 void init_2nd_DUART (void)
 {
-	NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
-	int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
+	NS16550_t console = (NS16550_t) CONFIG_SYS_NS16550_COM2;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE;
 
 	*(u8 *) (0xfc004511) = 0x1;
 	NS16550_init (console, clock_divisor);
@@ -84,7 +84,7 @@ phys_size_t initdram (int board_type)
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
@@ -147,12 +147,12 @@ void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
 void duart_setup (u32 base, u16 divisor)
 {
 	printf ("duart setup ...");
-	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x80);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 0), divisor & 0xff);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 1), divisor >> 8);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x03);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 4), 0x03);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 2), 0x07);
 	printf ("done\n");
 }