X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fnetstal%2Fhcu4%2Fhcu4.c;h=1c99405bea9cb4288f199c7e3342dae8cc3cbd4c;hb=61f2b38a17f5b21c59f2afe6cf1cbb5f28638cf9;hp=bb610e2d53de34b7cf6f3812d802467c9c7da9b3;hpb=74973126d1be63ac75bdc192f46234dca3a7c421;p=u-boot

diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c
index bb610e2d53..1c99405bea 100644
--- a/board/netstal/hcu4/hcu4.c
+++ b/board/netstal/hcu4/hcu4.c
@@ -22,7 +22,7 @@
 #include  <ppc4xx.h>
 #include  <asm/processor.h>
 #include  <asm/io.h>
-#include  <asm-ppc/u-boot.h>
+#include  <asm/u-boot.h>
 #include  "../common/nm.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * This function is run very early, out of flash, and before devices are
- * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
  * of being in the init_sequence array.
  *
  * The SDRAM has been initialized already -- start.S:start called
@@ -58,12 +58,12 @@ int board_early_init_f (void)
 	 *      IRQ 17-24 RESERVED/UNUSED
 	 *      IRQ 31 (EXT IRQ 6) (unused)
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-	mtdcr(uicer, 0x00000000); /* disable all ints */
-	mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
-	mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
-	mtdcr(uictr, 0x00000000); /* set int trigger levels */
-	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
+	mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
 	mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
 	mtdcr(CPC0_ECR, 0x60606000);
@@ -92,7 +92,7 @@ int checkboard (void)
 	u16 index      = boardVersReg & 0x0f;
 
 	/* Cannot be done in board_early_init */
-	mtdcr(cntrl0,  CPC0_CR0_VALUE);
+	mtdcr(CPC0_CR0,  CPC0_CR0_VALUE);
 
 	/* Force /RTS to active. The board it not wired quite
 	 *  correctly to use cts/rtc flow control, so just force the
@@ -120,15 +120,6 @@ void hcu_led_set(u32 value)
 	out_be32((u32 *)GPIO0_OR, tmp);
 }
 
-/*
- * sdram_init - Dummy implementation for start.S, spd_sdram  or initdram
- *		used for HCUx
- */
-void sdram_init(void)
-{
-	return;
-}
-
 /*
  * hcu_get_slot
  */
@@ -143,7 +134,7 @@ u32 hcu_get_slot(void)
  */
 u32 get_serial_number(void)
 {
-	u32 serial = in_be32((u32 *)CFG_FLASH_BASE);
+	u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
 
 	if (serial == 0xffffffff)
 		return 0;
@@ -163,7 +154,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
 	long dram_size = 0;
 	u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
@@ -183,17 +174,6 @@ long int initdram(int board_type)
 	return dram_size;
 }
 
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-	return 0;	/* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
-
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
@@ -201,3 +181,18 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = 1;
+		info->chipwidth = 1;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else
+		return 0;
+}