X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fnetta%2Fnetta.c;h=5c935f47a25c3d00ebb126ba1a24366c5fae3b0f;hb=5f4d36825a028e300b7d56a566d2cf84418b7a68;hp=afb3fe183325cf5b1ff5e53b2a138769406cf373;hpb=04a85b3b36fdbaaac5fa95d61f59f481bbcf7520;p=u-boot diff --git a/board/netta/netta.c b/board/netta/netta.c index afb3fe1833..5c935f47a2 100644 --- a/board/netta/netta.c +++ b/board/netta/netta.c @@ -35,6 +35,11 @@ #include #endif +int fec8xx_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +int fec8xx_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); + /****************************************************************/ /* some sane bit macros */ @@ -63,6 +68,11 @@ int checkboard(void) printf ("Intracom NETTA" #if defined(CONFIG_NETTA_ISDN) " with ISDN support" +#endif +#if defined(CONFIG_NETTA_6412) + " (DSP:TI6412)" +#else + " (DSP:TI6711)" #endif "\n" ); @@ -279,7 +289,7 @@ const uint sdram_table[0x40] = { #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) /* 8 */ -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) @@ -327,9 +337,9 @@ void check_ram(unsigned int addr, unsigned int size) } } -long int initdram(int board_type) +phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; @@ -345,10 +355,10 @@ long int initdram(int board_type) /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ udelay(200); @@ -426,12 +436,13 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - miiphy_read(phyno, PHY_PHYIDR1, &v); + fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); if (v == 0xFFFF) continue; - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD); + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); udelay(10000); - miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, + PHY_BMCR_RESET | PHY_BMCR_AUTON); udelay(10000); } } @@ -462,10 +473,10 @@ int last_stage_init(void) #define PA_SP_DIRVAL 0 #define PB_GP_INMASK (_B(28) | _B(31)) -#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 30)) +#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30)) #define PB_SP_MASK (_BR(22, 25)) #define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) +#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31)) #define PB_SP_DIRVAL 0 #define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15)) @@ -479,12 +490,22 @@ int last_stage_init(void) #define PD_GP_INMASK 0 #define PD_GP_OUTMASK _BWR(3, 15) #define PD_SP_MASK 0 + +#if defined(CONFIG_NETTA_6412) + +#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15)) + +#else + #define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11)) + +#endif + #define PD_SP_DIRVAL 0 int board_early_init_f(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile iop8xx_t *ioport = &immap->im_ioport; volatile cpm8xx_t *cpm = &immap->im_cpm; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -492,11 +513,15 @@ int board_early_init_f(void) /* CS1: NAND chip select */ memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ; memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); - +#if !defined(CONFIG_NETTA_6412) /* CS2: DSP */ memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - +#else + /* CS6: DSP */ + memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); + memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); +#endif /* CS4: External register chip select */ memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); @@ -525,27 +550,12 @@ int board_early_init_f(void) ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; ioport->iop_pdpar = PD_SP_MASK; - ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); + /* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */ return 0; } -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#include - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen = nand_probe(CFG_NAND_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#if defined(CONFIG_CMD_PCMCIA) int pcmcia_init(void) { @@ -554,17 +564,6 @@ int pcmcia_init(void) #endif -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return 0; /* No hotkeys supported */ -} -#endif - #ifdef CONFIG_HW_WATCHDOG void hw_watchdog_reset(void)