X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fnx823%2Fnx823.c;h=7867fff67b81d1876391ad2c087bf205e1510cd6;hb=76756e41cde0a617e781a604cc47dfaef63697cd;hp=65d45c197f0053cc6ad9c4c1d4ca036a818f9167;hpb=038ccac511214b062c56f22b9413f784b86bcd87;p=u-boot diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c index 65d45c197f..7867fff67b 100644 --- a/board/nx823/nx823.c +++ b/board/nx823/nx823.c @@ -27,13 +27,12 @@ #include #include #include +#include -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; static long int dram_size (long int, long int *, long int); -/* ------------------------------------------------------------------------- */ - #define _NOT_USED_ 0xFFFFFFFF const uint sdram_table[] = { @@ -159,9 +158,9 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size_b1, size8, size9; @@ -172,22 +171,22 @@ long int initdram (int board_type) * Up to 2 Banks of 64Mbit x 2 devices * Initial builds only have 1 */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; memctl->memc_mar = 0x00000088; /* * Map controller SDRAM bank 0 */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* * Map controller SDRAM bank 1 */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; /* * Perform SDRAM initializsation sequence @@ -211,7 +210,7 @@ long int initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; @@ -221,7 +220,7 @@ long int initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -229,7 +228,7 @@ long int initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -237,7 +236,7 @@ long int initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -260,7 +259,7 @@ long int initdram (int board_type) */ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } @@ -270,9 +269,9 @@ long int initdram (int board_type) if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b0 > 0) { /* @@ -280,9 +279,9 @@ long int initdram (int board_type) */ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | - CFG_OR_TIMING_SDRAM; + CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br1 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b1; } else { @@ -297,16 +296,16 @@ long int initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } else { /* SDRAM Bank 0 is bigger - map first */ memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br1 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b1 > 0) { /* @@ -314,9 +313,9 @@ long int initdram (int board_type) */ memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | - CFG_OR_TIMING_SDRAM; + CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b0; } else { @@ -331,7 +330,7 @@ long int initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } @@ -354,7 +353,7 @@ long int initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -362,43 +361,30 @@ static long int dram_size (long int mamr_value, long int *base, return (get_ram_size (base, maxsize)); } -u_long *my_sernum; - int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; - + int i; char tmp[50]; - u_char *e = gd->bd->bi_enetaddr; + uchar ethaddr[6]; + bd_t *bd = gd->bd; + ulong *my_sernum = (unsigned long *)&bd->bi_sernum; - /* save serial numbre from flash (uniquely programmed) */ - my_sernum = malloc (8); - memcpy (my_sernum, gd->bd->bi_sernum, 8); + /* load unique serial number */ + for (i = 0; i < 8; ++i) + bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i); /* save env variables according to sernum */ sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]); setenv ("serial#", tmp); - sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3], - e[4], e[5]); - setenv ("ethaddr", tmp); - return (0); -} - -void load_sernum_ethaddr (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int i; - bd_t *bd = gd->bd; - - for (i = 0; i < 8; i++) { - bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i); + if (!eth_getenv_enetaddr("ethaddr", ethaddr)) { + ethaddr[0] = 0x10; + ethaddr[1] = 0x20; + ethaddr[2] = 0x30; + ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2]; + ethaddr[4] = bd->bi_sernum[5]; + ethaddr[5] = bd->bi_sernum[6]; } - bd->bi_enetaddr[0] = 0x10; - bd->bi_enetaddr[1] = 0x20; - bd->bi_enetaddr[2] = 0x30; - bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2]; - bd->bi_enetaddr[4] = bd->bi_sernum[5]; - bd->bi_enetaddr[5] = bd->bi_sernum[6]; + + return 0; }