X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fpcs440ep%2Fpcs440ep.c;h=5a3ec584451bbd502cdce86a69f50a3bf95e8f58;hb=711a6722f97d21404d04c7a36ccfdc6e2b442229;hp=929375987cc8808d07e59c05a9460cc9bb464128;hpb=1095493a5d4c16f481a783f6f54d83ad0e07dfa0;p=u-boot

diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 929375987c..5a3ec58445 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -22,7 +22,7 @@
  */
 
 #include <common.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <malloc.h>
 #include <command.h>
 #include <crc.h>
@@ -148,7 +148,7 @@ int board_early_init_f(void)
 	mtdcr(EBC0_CFGDATA, reg | 0x04000000);	/* Set ATC */
 
 	/*--------------------------------------------------------------------
-	 * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
+	 * GPIO's are alreay setup in arch/powerpc/cpu/ppc4xx/cpu_init.c
 	 * via define from board config file.
 	 *-------------------------------------------------------------------*/
 
@@ -509,12 +509,13 @@ int misc_init_r (void)
 
 int checkboard(void)
 {
-	char *s = getenv("serial#");
+	char buf[64];
+	int i = getenv_f("serial#", buf, sizeof(buf));
 
 	printf("Board: PCS440EP");
-	if (s != NULL) {
+	if (i > 0) {
 		puts(", serial# ");
-		puts(s);
+		puts(buf);
 	}
 	putc('\n');
 
@@ -550,82 +551,6 @@ phys_size_t initdram (int board_type)
 	return dram_size;
 }
 
-/*************************************************************************
- *  pci_pre_init
- *
- *  This routine is called just prior to registering the hose and gives
- *  the board the opportunity to check things. Returning a value of zero
- *  indicates that things are bad & PCI initialization should be aborted.
- *
- *	Different boards may wish to customize the pci controller structure
- *	(add regions, override default access routines, etc) or perform
- *	certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
-	unsigned long addr;
-
-	/*-------------------------------------------------------------------------+
-	  | Set priority for all PLB3 devices to 0.
-	  | Set PLB3 arbiter to fair mode.
-	  +-------------------------------------------------------------------------*/
-	mfsdr(SD0_AMP1, addr);
-	mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
-	addr = mfdcr(PLB3_ACR);
-	mtdcr(PLB3_ACR, addr | 0x80000000);
-
-	/*-------------------------------------------------------------------------+
-	  | Set priority for all PLB4 devices to 0.
-	  +-------------------------------------------------------------------------*/
-	mfsdr(SD0_AMP0, addr);
-	mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
-	addr = mfdcr(PLB4_ACR) | 0xa0000000;	/* Was 0x8---- */
-	mtdcr(PLB4_ACR, addr);
-
-	/*-------------------------------------------------------------------------+
-	  | Set Nebula PLB4 arbiter to fair mode.
-	  +-------------------------------------------------------------------------*/
-	/* Segment0 */
-	addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
-	addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
-	addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
-	addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
-	mtdcr(PLB0_ACR, addr);
-
-	/* Segment1 */
-	addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
-	addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
-	addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
-	addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
-	mtdcr(PLB1_ACR, addr);
-
-	return 1;
-}
-#endif	/* defined(CONFIG_PCI) */
-
-/*************************************************************************
- *  pci_master_init
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
-	unsigned short temp_short;
-
-	/*--------------------------------------------------------------------------+
-	  | Write the PowerPC440 EP PCI Configuration regs.
-	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
-	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
-	  +--------------------------------------------------------------------------*/
-	pci_read_config_word(0, PCI_COMMAND, &temp_short);
-	pci_write_config_word(0, PCI_COMMAND,
-			      temp_short | PCI_COMMAND_MASTER |
-			      PCI_COMMAND_MEMORY);
-}
-#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
 /*************************************************************************
  *  hw_watchdog_reset
  *
@@ -643,7 +568,7 @@ void hw_watchdog_reset(void)
  * "led" Commando for the U-Boot shell
  *
  ************************************************************************/
-int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int	rcode = 0, i;
 	ulong	pattern = 0;
@@ -687,14 +612,13 @@ U_BOOT_CMD(
  * "sha1" Commando for the U-Boot shell
  *
  ************************************************************************/
-int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int	rcode = -1;
 
 	if (argc < 2) {
-  usage:
-		cmd_usage(cmdtp);
-		return 1;
+usage:
+		return cmd_usage(cmdtp);
 	}
 
 	if (argc >= 3) {