X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fprodrive%2Falpr%2Ffpga.c;h=f3bc1fa7a1693c291a46f86ba796f53bd57edc10;hb=83653121d7382fccfe329cb732f77f116341ef1d;hp=78307b486b0bafe210c7489c8013e5b154c2fab9;hpb=64cd52efd1dc51a4a5a0cf10efe5362fab27de29;p=u-boot

diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c
index 78307b486b..f3bc1fa7a1 100644
--- a/board/prodrive/alpr/fpga.c
+++ b/board/prodrive/alpr/fpga.c
@@ -30,13 +30,13 @@
 #include <altera.h>
 #include <ACEX1K.h>
 #include <command.h>
-#include <asm-ppc/processor.h>
+#include <asm/processor.h>
 #include <ppc440.h>
 #include "fpga.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (CONFIG_FPGA)
+#if defined(CONFIG_FPGA)
 
 #ifdef FPGA_DEBUG
 #define	PRINTF(fmt,args...)	printf (fmt ,##args)
@@ -44,46 +44,38 @@ DECLARE_GLOBAL_DATA_PTR;
 #define	PRINTF(fmt,args...)
 #endif
 
-static	unsigned long	regval;
+static unsigned long regval;
 
-#define SET_GPIO_REG_0(reg, bit) {\
-					regval = in32(reg);\
-					regval &= ~(0x80000000 >> bit);\
-					out32(reg, regval);\
-					}
-
-#define SET_GPIO_REG_1(reg, bit) {\
-					regval = in32(reg);\
-					regval |= (0x80000000 >> bit);\
-					out32(reg, regval);\
-					}
-
-#define	GPIO_CLK_PIN			0x00002000
-#define	GPIO_CLK_PIN_I			0xffffdfff
-#define GPIO_DAT_PIN			0x00001000
-#define GPIO_DAT_PIN_I			0xffffefff
-#define GPIO_CLKDAT_PIN_I		0xffffcfff
+#define SET_GPIO_REG_0(reg, bit) {				\
+		regval = in32(reg);				\
+		regval &= ~(0x80000000 >> bit);			\
+		out32(reg, regval);				\
+	}
 
-#define SET_GPIO_CLK_0			out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLK_PIN_I);
-#define SET_GPIO_CLK_1			out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_CLK_PIN);
-#define SET_GPIO_DAT_0			out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_DAT_PIN_I);
-#define SET_GPIO_DAT_1			out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_DAT_PIN);
+#define SET_GPIO_REG_1(reg, bit) {				\
+		regval = in32(reg);				\
+		regval |= (0x80000000 >> bit);			\
+		out32(reg, regval);				\
+	}
 
-#define	SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
-#define	SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
+#define	SET_GPIO_0(bit)		SET_GPIO_REG_0(GPIO0_OR, bit)
+#define	SET_GPIO_1(bit)		SET_GPIO_REG_1(GPIO0_OR, bit)
 
-#define SET_GPIO_CLK_0_Z1		out32(GPIO0_OR, (in32(GPIO0_OR) & GPIO_CLK_PIN_I) | GPIO_DAT_PIN);
-#define SET_GPIO_CLK_0_Z0		out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLKDAT_PIN_I);
+#define FPGA_PRG		(0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
+#define FPGA_CONFIG		(0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
+#define FPGA_DATA		(0x80000000 >> CONFIG_SYS_GPIO_DATA)
+#define FPGA_CLK		(0x80000000 >> CONFIG_SYS_GPIO_CLK)
+#define OLD_VAL			(FPGA_PRG | FPGA_CONFIG)
 
-#define FPGA_WRITE_1 { \
-			SET_GPIO_CLK_0_Z1\
-			SET_GPIO_CLK_1}
+#define SET_FPGA(data)		out32(GPIO0_OR, data)
 
-#define FPGA_WRITE_0 { \
-			SET_GPIO_CLK_0_Z0\
-			SET_GPIO_CLK_1}
+#define FPGA_WRITE_1 {							\
+		SET_FPGA(OLD_VAL | 0        | FPGA_DATA);  /* set data to 1  */	\
+		SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
 
-#define P_GP(reg) (reg & 0x00023f00)
+#define FPGA_WRITE_0 {							\
+		SET_FPGA(OLD_VAL | 0        | 0        );   /* set data to 0  */ \
+		SET_FPGA(OLD_VAL | FPGA_CLK | 0        );}  /* set data to 1  */
 
 /* Plattforminitializations */
 /* Here we have to set the FPGA Chain */
@@ -95,43 +87,43 @@ int fpga_pre_fn (int cookie)
 
 	reg = in32(GPIO0_IR);
 	/* Enable the FPGA Chain */
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN);
-	SET_GPIO_1(CFG_GPIO_PROG_EN);
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR);
-	SET_GPIO_0((CFG_GPIO_SEL_DPR));
-
-	/* initialize the GPIO Pins */	
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
+	SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
+	SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
+
+	/* initialize the GPIO Pins */
 	/* output */
-	SET_GPIO_0(CFG_GPIO_CLK);
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK);
+	SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
 
 	/* output */
-	SET_GPIO_0(CFG_GPIO_DATA);
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA);
+	SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
 
 	/* First we set STATUS to 0 then as an input */
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
-	SET_GPIO_0(CFG_GPIO_STATUS);
-	SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
 
 	/* output */
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG);
-	SET_GPIO_0(CFG_GPIO_CONFIG);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
+	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
 
 	/* input */
-	SET_GPIO_0(CFG_GPIO_CON_DON);
-	SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON);
+	SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
+	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
 
 	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
-	SET_GPIO_0(CFG_GPIO_CONFIG);
+	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
 	return FPGA_SUCCESS;
 }
 
@@ -139,9 +131,9 @@ int fpga_pre_fn (int cookie)
 int fpga_config_fn (int assert_config, int flush, int cookie)
 {
 	if (assert_config) {
-		SET_GPIO_1(CFG_GPIO_CONFIG);
+		SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
 	} else {
-		SET_GPIO_0(CFG_GPIO_CONFIG);
+		SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
 	}
 	return FPGA_SUCCESS;
 }
@@ -152,7 +144,7 @@ int fpga_status_fn (int cookie)
 	unsigned long	reg;
 
 	reg = in32(GPIO0_IR);
-	if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) {
+	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
 		PRINTF("STATUS = HIGH\n");
 		return FPGA_FAIL;
 	}
@@ -165,7 +157,7 @@ int fpga_done_fn (int cookie)
 {
 	unsigned long	reg;
 	reg = in32(GPIO0_IR);
-	if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) {
+	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
 		PRINTF("CONF_DON = HIGH\n");
 		return FPGA_FAIL;
 	}
@@ -174,7 +166,7 @@ int fpga_done_fn (int cookie)
 }
 
 /* writes the complete buffer to the FPGA
-   writing the complete buffer in one function is very faster,
+   writing the complete buffer in one function is much faster,
    then calling it for every bit */
 int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
 {
@@ -182,14 +174,10 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
 	unsigned char *data = (unsigned char *) buf;
 	unsigned char val=0;
 	int		i;
+	int len_40 = len / 40;
 
 	while (bytecount < len) {
-#ifdef CFG_FPGA_CHECK_CTRLC
-		if (ctrlc ()) {
-			return FPGA_FAIL;
-		}
-#endif
-		val = data[bytecount ++ ];
+		val = data[bytecount++];
 		i = 8;
 		do {
 			if (val & 0x01) {
@@ -201,9 +189,14 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
 			i --;
 		} while (i > 0);
 
-#ifdef CFG_FPGA_PROG_FEEDBACK
-		if (bytecount % (len / 40) == 0)
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+		if (bytecount % len_40 == 0) {
 			putc ('.');		/* let them know we are alive */
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc ())
+				return FPGA_FAIL;
+#endif
+		}
 #endif
 	}
 	return FPGA_SUCCESS;
@@ -212,7 +205,7 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
 /* called, when programming is aborted */
 int fpga_abort_fn (int cookie)
 {
-	SET_GPIO_1((CFG_GPIO_SEL_DPR));
+	SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
 	return FPGA_SUCCESS;
 }
 
@@ -251,8 +244,8 @@ int alpr_fpga_init (void)
 {
 	int i;
 
-	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
-	fpga_init (gd->reloc_off);
+	PRINTF ("%s:%d: Initialize FPGA interface\n", __FUNCTION__, __LINE__);
+	fpga_init ();
 
 	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
 		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);